Quicklogic Corporation

Monolithic Memories, Inc.

Advanced Micro Devices Corporation

Other

John M Birkner

Andrew K Chan

Hua-Thye Chua

Mammen Thomas

Ralph G Whitten

Richard L Bechtel

Hua T Chua

Sing Y Wong

Robert C Ghest

Michael J Miller

Richard J Wong

William D Cox

Albert L Chan

Warren K Miller

Shlomo Waser

Danesh M Tavana

David T Martin

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Method for fabrication of programmable interconnect structure

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Programmable application specific integrated circuit and logic cell

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Electrically programmable interconnect structure having a PECVD

A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Field programmable gate array having reproducible metal-to-metal

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

In a field programmable gate array, a plurality of wire segments extend parallel to each other between two logic cells. Some of the wire segments extend to logic cell inputs and others to logic cell outputs. A power wire extends perpendicular to the wire segments and crosses each of the wire segments. Antifuses are disposed to couple the input wire segments to the power wire but no antifuses are disposed between the output wire segments and the power wire.

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ('modules') integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device. The method comprises the steps of: 1) before the antifuse is programmed, determining an electrical characteristic (such as a voltage, current and/or resistance) of a first conductive path which includes a series element disposed electrically in series with a parallel element, the parallel element being controlled to be substantially conductive, the parallel element being disposed electrically in parallel with the unprogrammed antifuse; 2) after programming of the antifuse, determining an electrical characteristic (such as a voltage, current and/or resistance) of a second conductive path including the series element disposed electrically in series with the programmed antifuse when the parallel element is controlled to be substantially nonconductive; 3) determining an electrical characteristic (such as a voltage, current and/or resistance) of a third, conductive path through the series element, and through the programmed antifuse and the parallel element, the parallel element being controlled to be substantially conductive; and 4) determining the electrical characteristic (such as a resistance) of the antifuse based on the above three determinations in 1), 2) and 3). The method is usable to determine whether or not programmed antifuses of a programmable device have low enough resistances to meet desired reliability criteria.

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Portola Valley, CA, United States of America

John M Birkner