Texas Instruments Corporation

John M Bach

David A Thomas

Rand B Carawan

Hemant Joshi

Sridhar Vajapey

Paul William Krause

A computer method of analyzing an integrated circuit ('IC') masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.

Determining feasibility of IC edits

A method of cross-mapping integrated circuit ('IC') elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.

Method of cross-mapping integrated circuit design formats

A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input connected to said third output signal of said first input exclusive not OR circuit and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal of said first shift register latch and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a first cell output signal, and at least one second register cell having a second input multiplexer for selecting between two input signals responsive to said one or more control signals and having a seventh output signal, a second input exclusive not OR circuit having a first input connected to said seventh output signal of said second input multiplexer and a second input connected to a cell output signal and having an eighth output signal, and a second shift register latch having an input connected to said eighth output signal of said second input exclusive not OR circuit and having a second cell output signal.

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Sugar Land, TX, United States of America

John M Bach