Lsi Logic Corporation

Avago Technologies International Sales Pte. Limited

Broadcom Corporation

John Lynn McNitt

Scott C Savage

Sean Anthony Golliher

Jay Edward Ackerman

John S Walley

Mark David Rutherford

Brett D Hardy

Marc Keppler

Russell Eliot Radke

Rishi Agarwal

Kerry Thompson

Kevin Vannorsdel

Yongjie Jiang

Michael Braiman

Arun Palaniappan

A system may include an adapter, a charger, and a connector. The adapter is configured to receive an alternating current (AC) signal and generate an adapter signal, the adapter signal being generated based on an up-conversion of the AC signal. The charger is configured to generate a direct current (DC) signal from the adapter signal using one or more energy storage elements and supply the DC signal to a load, in which the adapter signal has a voltage greater than that of the DC signal. The connector is configured to couple the adapter and the charger. In some aspects, the adapter signal is adjusted based on one or more measurements of the DC signal at an output of the charger to maintain a target power for charging the load.

Battery charging architectures

A multi-loop voltage regulator with load tracking compensation includes a first closed-loop feedback network configured to receive a supply voltage from a power supply and drive an output voltage that is smaller than the supply voltage to a load. The multi-loop voltage regulator includes a second closed-loop feedback network connected to the first closed-loop feedback network and configured to regulate the output voltage between a first supply voltage rail and a second supply voltage rail for a given load current, in which the second closed-loop feedback network produces a gain that is greater than that of the first closed-loop feedback network. The multi-loop voltage regulator also includes a load tracking compensation circuit configured to detect a load current, and to increase the gain of the second closed-loop feedback network based on a dominant pole in the second closed-loop feedback network being a function of the detected load current.

Multi-loop voltage regulator with load tracking compensation

A power management unit accurately measures and controls charging current. The power management unit may be implemented more efficiently than prior designs, leading to cost savings in the implementation of the power management unit as well as in the implementation of the device that incorporates the power management unit. The power management unit incorporates a model of an external charge control device (e.g., a transistor) and uses that model in a way that allows the power management unit to eliminate external device pins and other circuitry.

Charger external power device gain sampling

A method and apparatus are provided for measuring high speed glitch energy between first and second. The method and apparatus induce a change in charge on the first node from a first charge level to a second charge level with glitch energy supplied by the second node. An amount of charge is then supplied to the first node to restore the charge on the first node from the second charge level toward the first charge level. A representation of the amount of charge supplied to the first node is measured.

Method and apparatus for measuring high speed glitch energy in an integrated circuit

On-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuits are provided. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value. The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip. A computer device reads each counter value and calculates mismatch values based on the counter values.

Method and integrated circuit for capacitor measurement with digital readout

A resistance measurement circuit includes a plurality of current sources, a plurality of resistor strings and a comparator. Each resistor string is coupled in series with a respective one of the current sources and includes a plurality of nodes with different resistances relative to a reference node. Each node in each resistor string has a different resistance relative to the reference node than corresponding nodes in the other resistor strings. The comparator has a first comparison input coupled to a reference voltage and a second comparison input selectively coupled to the plurality of nodes in each resistor string.

Method and apparatus for measuring sheet resistance

Systems and methods for enhancing slew control of output signals. An output driver receives an input signal and controllably increases the gain of that signal to provide a high quality output signal for use by an electronic device coupled thereto. The output driver includes an operational amplifier that maintains stability of the output signal through a feedback of the output signal. A control circuit supplies a signal to the output driver such that the driver to improve the shape of the output signal as the input signal is applied. After the operational amplifier regains control, the control circuit disengages. One embodiment of the present invention may be particularly useful as a USB output driver.

Method and apparatus for slew control of an output signal

An apparatus comprising a control circuit and a logic circuit. The control circuit may be configured to receive an input signal and an indication signal and present a complement of the input signal. The logic circuit may be configured to receive the complementary input signal and generate an output signal. The output signal may provide full scale voltages between a first supply (e.g., VSS) and a second supply (e.g., VDD ).

Inverting level shifter with start-up circuit

A termination impedance in a semiconductor circuit is trimmed to fall within a desired range by a trimming circuit such that the amount of variation in the termination impedance is less than the variation in the sheet rho (resistivity) of the semiconductor. An external reference resistor causes a reference current to flow in multiple branches of a current mirror circuit. One branch of the current mirror circuit has a resistance less than the reference resistor, another has a resistance approximately equal to the reference resistor, and another has resistance greater than the reference resistor. Variation in the sheet rho results voltage drops across the resistor in variation in the resistor values. A logic circuit detects the variations, and encodes a control signal. The control signal is received by a variable termination circuit that switches parallel resistance branches in or out of the termination impedance circuit such that an effective termination impedance is selected based upon the control signal. The resulting termination impedance is thereby maintained within a higher tolerance range than the variation in the termination impedance that would otherwise result from sheet rho variation. 37 CFR 1.72( ).

Growing community of inventors

Fort Collins, CO, United States of America

John Lynn McNitt