Texas Instruments Corporation

John Ling So

Steven R Magee

Jeffrey L Kerr

An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

PC circuits, systems and methods

An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.

Data transfer circuitry, DSP wrapper circuitry and improved processor

An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230). The bus bridge (2236), the bus interface (2220) and the first terminals and the DRAM memory controller (2250) have datapaths selectively interconnected in response to the arbiter circuit (2230). Other devices, systems and methods are also disclosed.

Bus bridge device including data bus of first width for a first

A DTMF receiver (10) recognizes each of a plurality of multi-frequency tones, each tone centered on a predetermined standard frequency. Two digital bandpass filters (14, 16) each have four frequency bins, each frequency bin operating according to a recursive second-order transfer function for preferentially transmitting frequencies near the standard frequencies. Each frequency bin accumulates, for each of a plurality of sampling periods, respective spectral energy signals from the input signal. A temporal energy signal is derived from the spectral energy signals. For each bandpass filter (14,16), a time-domain test template generator (30) and a frequency-domain test template generator (34) are provided to generate time-domain and frequency-domain test templates. These test templates are input to an analyzer (38) that compares the templates against data-adaptive frequency-domain and time-domain reference templates.

DTMF receiver

A DTMF receiver (10) recognizes each of a plurality of multi-frequency tones, each tone centered on a predetermined standard frequency. Two digital bandpass filters (14, 16) each have four frequency bins, each frequency bin operating according to a recursive second-order transfer function for preferentially transmitting frequencies near the standard frequencies. Each frequency bin accumulates, for each of a plurality of sampling periods, respective spectral energy signals from the input signal. A temporal energy signal is derived from the spectral energy signals. For each bandpass filter (14, 16), a time-domain test template generator (30) and a frequency-domain test template generator (34) are provided to generate time-domain and frequency-domain test templates. These test templates are input to an analyzer (38) that compares the templates against data-adaptive frequency-domain and time-domain reference templates.

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Plano, TX, United States of America

John Ling So