Alliedsignal Inc.

John Lin

Andras F Cserhati

A high performance lateral Silicon-On-Insulator (SOI) power device having a high breakdown voltage (.ltoreq.100 v). The SOI power device includes a silicon layer formed on an oxide layer over a silicon substrate. A mask having a single opening on the anode (drain) side of the silicon layer is formed thereon such that an impurity may be introduced into the silicon layer. The resultant dopant is implanted in the anode side and laterally diffused by high temperature annealing. The resultant device sustains breakdown voltages of up to 100 volts and enables an extremely low on-state resistance of 1.2 milliohm-cm.sup.2.

Method of fabricating improved lateral Silicon-On-Insulator (SOI) power

A method for making all complementary BiCDMOS devices on a SOI substrate (10). Isolated n.sup.- and p.sup.- regions (20,32,34,36,40,42) are formed on the silicon layer (16) and oxidized. LOCOS oxide regions (28) are formed on selected pairs of the n.sup.- and p.sup.- regions on which gates (44) for complementary DMOS device (114,116) and field plates (46) for complementary bipolar devices (118,120) are formed. Gates (48) for complementary MOS devices (122,124) are formed directly on the oxidized silicon layer (24). N-type and p-type dopants are then implanted into the silicon layer (16) forming n body and p body areas (54,56,58,60). Selected n.sup.+ and p.sup.+ areas (66,68) are formed in the n body and p body areas (54,56,58,60) as well as selected areas of n.sup.- and p.sup.- regions (30,32,34,36,40,42). The substrate (10) is then covered with an oxide layer and windows etched therethrough to expose said n.sup.+ and p.sup.+ areas (66,68) and selected areas of the gates (44,48) and field plates (46). Metal electrical contacts (78-112) are deposited through the windows to the n.sup.+ and p.sup.+ areas ( 66,68) and the gates (44,48) and field plates (46).

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Ellicott City, MD, United States of America

John Lin