Cadence Design Systems, Inc.

John LeRoy Pierce

Daniel Asher Cohen

Petr William Spacek

Nir Weiss

Prasanna Rao

Adam D Sherer

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiments may further include calculating configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design. Embodiments may also include determining a change in the one or more memory elements and altering a function associated with the electronic design verification based upon, at least in part, the determined change.

System, method, and computer program product for electronic design configuration space determination and verification

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing, using one or more processors, an electronic design verification environment having a plurality of randomize calls associated therewith. Embodiments can also include selecting one of the plurality of randomize calls for analysis at a constraint solver engine and iteratively analyzing the selected randomize call using a plurality of constraint solver algorithms. Embodiments can also include automatically determining a most effective constraint solver algorithm for the selected randomize call.

System, method, and computer program product for automatically selecting a constraint solver algorithm in a design verification environment

The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design. The method may also include associating, using the at least one computing device, an identifier with each constraint solver call utilized in a simulation of the electronic design. The method may also include generating, using the at least one computing device, an application programming interface configured to allow a user to navigate through electronic design simulation results based upon, at least in part, the identifier associated with each constraint solver call.

System and method for identifying constraint solver calls

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiment may also include calculating, using one or more processors, configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design. Embodiments may further include storing a seed for each configuration, wherein each seed may be configured to cause a constraint solver to set a defined set of values for one or more random variables in a class associated with the seed.

System, method, and computer program product for ensuring that each simulation in a regression is running a unique configuration

The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design and associating, using the at least one computing device, one or more identifiers with each constraint solver call utilized in a simulation of the electronic design. The method may further include automatically generating, using the at least one computing device, a coverage model for one of more constraints associated with the electronic design, the coverage model being based upon, at least in part, the one or more identifiers.

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Temple, NH, United States of America

John LeRoy Pierce