Advanced Micro Devices Corporation

John Lee Nistler

Stuart E Brown

Charles E May

Mark W Michael

Mark I Gardner

Derick J Wristers

Frederick N Hause

Michael G McIntyre

Christopher H Raeder

Iraj Emami

Richard W Jarvis

John D Spano

Phillip J Etter

Kenneth J Morrissey

A method for forming a photomask includes providing a transparent substrate and forming an opaque layer over at least a first portion of the transparent substrate. The opaque layer is patterned to define a mask pattern and expose at least a second portion of the transparent substrate. The second portion is etched to define a phase shifting region. The width of the phase shifting region defines a critical dimension. The critical dimension is measured, and the phase shifting region is etched based on the critical dimension to undercut the optically opaque layer. A photomask includes a transparent substrate and a phase shifting region defined in the transparent substrate. The phase shifting region includes sloped sidewalls having a slope of less than about 85&deg;.

Phase-shift photomask for patterning high density features

A metallization system ( ) suitable for use in a semiconductor component and a method for fabricating the metallization system ( ). The metallization system ( ) includes a dielectric material ( ) disposed on a major surface ( ) of a substrate ( ). The dielectric material ( ) contains a dielectric filled plug ( ) over a conductor ( ). A metal filled plug ( ) extends through the dielectric filled plug ( ). The metal of the metal filled plug ( ) electrically contacts the conductor ( ). The metallization system ( ) may be fabricated by etching a via ( ) in the dielectric material ( ) and filling the via ( ) with a dielectric material ( ) having a dielectric constant that is greater than the dielectric constant of the dielectric material ( ) disposed on the major surface. A via ( ) is formed in the dielectric material ( ) that fills the via ( ) and the via ( ) is filled with a metal.

Metallization system for use in a semiconductor component

A photomask includes a transparent substrate, a line patterning feature having ends formed on the transparent substrate, and an island patterning feature adjacent at least one of the ends of the line patterning feature. A method for fabricating a feature on a wafer includes providing a photomask. The photomask includes a transparent substrate, a line patterning feature having ends formed on the transparent substrate, and an island patterning feature adjacent at least one of the ends of the line patterning feature. A radiation source adapted to supply incident radiation is provided, and a wafer is exposed with the incident radiation through the photomask.

Semiconductor feature having support islands

Various methods of inspecting a film on a semiconductor workpiece for a residue are provided. In one aspect, a method of inspecting a film on a semiconductor workpiece wherein the film has a known infrared signature is provided. The method includes heating the workpiece so that the film emits infrared radiation and sensing the infrared radiation emitted from the film. The infrared signature of the radiation emitted from the film is compared with the known infrared signature and a signal indicative of a deviation between the infrared signature of the emitted infrared radiation and the known infrared signature is generated. The method enables the rapid and accurate detection of residues, such as oxide residues on nitride films.

Infrared inspection for determining residual films on semiconductor devices

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines when the test structure is inspected. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure. The electrical testing may be used to validate the voltage contrast methodology, as well as determine the approximate size of defects formed on the test structure.

Multipurpose defect test structure with switchable voltage contrast capability and method of use

A computer-implemented method is provided in which a design layer of an integrated circuit is altered by spatial definition using underlying and overlying design layers. That is, the specific layers of an integrated circuit that impact the layer being modified are taken into account. According to an embodiment, the computer-implemented method is performed using, e.g., a CAD program. First, an original layout design comprising a plurality of design layers representing respective levels of an integrated circuit is generated. The targeted properties, e.g., electrical properties, of features in one design layer are determined based upon the arrangement of features in other design layers relative to the features in that one design layer. The features in the design layer being modified are then separated into different working layers such that each working layer includes features having at least one common targeted property. The features in each working layer may then be separately modified based upon the mutual targeted property of that working layer.

Modifying a design layer of an integrated circuit using overlying and underlying design layers

A self-aligned semiconductor device including a high-K dielectric which is not exposed to elevated processing temperatures and a method for producing this device are provided. The method may also be used to fabricate a test structure, with which multiple combinations of gate dielectric/conductor configurations may be tested quickly and inexpensively. A self-aligned transistor is fabricated on a semiconductor substrate. Protective dielectrics are subsequently formed over the substrate and surrounding the transistor gate conductor such that upper surfaces of the dielectrics are even with the upper surface of the gate conductor. This dielectric-protected transistor forms a test structure which may be used to evaluate various gate dielectric/conductor configurations. The test structure is formed relatively simply using only two masking steps, and is believed to be particularly suited for evaluation of high-K gate dielectric configurations. The transistor gate conductor may be subsequently removed without disturbing the rest of the transistor. The removed gate conductor may be replaced with materials including high-K dielectrics, metals, and polysilicon. Because source and drain regions are formed before formation of the protective dielectrics, the gate dielectric/conductor materials used to replace the original gate conductor are not exposed to the elevated temperatures which may be used for impurity introduction.

Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices

The present invention is directed to a method for determining changes in electrical characteristics of semiconductor devices due to the fabrication of the devices in proximity to other devices or structures. The method comprises fabricating a plurality of semiconductor devices configured in a series arrangement and biasing all but one of the semiconductor devices to an active state. Thereafter, the remaining semiconductor device is biased to an active state and the electrical characteristics of the last semiconductor device is monitored.

Method for determining proximity effects on electrical characteristics of semiconductor devices

A transistor and transistor fabrication method are presented in which a graded junction is formed using a plurality of source/drain dopant implants. The implants are performed such that higher concentrations of dopant species are implanted at lower energies and lower dopant concentrations are implanted at higher energies. In an embodiment, an anneal step is used to create the graded junction by exploiting the concentration dependence of the dopant diffusivity (i.e., dopant species implanted in regions of high concentration are more mobile than dopant species implanted in regions of low concentration). Sub-0.25-micron transistors formed by the process described herein may be less susceptible to deleterious capacitive loading and parasitic resistance than transistors having conventionally formed lightly doped drain and source/drain implants. Transistors formed according to the method of this application may also advantageously include highly doped shallow junctions while incorporating lightly doped deeper junctions to avoid the problem of junction spiking. Integrated circuits including transistors formed according to the method described herein may further be subject to less inter-transistor variation in effective channel length, and therefore threshold voltage roll-off and drive current variability, than integrated circuits including conventionally formed transistors.

Fabrication of a non-ldd graded p-channel mosfet

A method of adjusting drive currents on a semiconductor device having transistors of various densities is disclosed. Consistent with the invention, off-state currents and drive currents associated with non-dense transistors on a first semiconductor device formed by a fabrication process are determined. Off-state currents associated with dense transistors on the first semiconductor device are also determined. Using the determined off-state and drive currents associated with the non-dense transistors and the off-state currents associated with the dense transistors on the first semiconductor device, drive currents associated with the dense transistors on the first semiconductor device are estimated. One or more parameters of the fabrication process are then adjusted based on the estimated drive currents of the dense transistors on the first semiconductor device in order to calibrate drive currents of dense transistors with drive currents of non-dense transistors on semiconductor devices formed using the fabrication process. The drive currents of the dense and non-dense transistors may, for example, be matched to within about 3 microamps.

Method of adjusting currents on a semiconductor device having

An integrated circuit fabrication process is provided for implanting silicon into select areas of a refractory metal to reduce the consumption of silicon-based junctions underlying those select areas during salicide formation. The refractory metal is subjected to a heat cycle to form salicide upon the junctions and polycide upon the upper surface of a gate conductor positioned between the junctions. In response to being heated, the metal atoms readily react with implanted silicon atoms positioned proximate the metal atoms to form salicide. Once a metal atom has reacted with implanted silicon atoms, it is no longer available to react with silicon atoms of the junctions. However, not all of the metal atoms react with implanted silicon atoms, so some of the metal atoms are free to react with the silicon atoms of the junctions. Interdiffusion and reaction between those available metal atoms and those silicon atoms of the junctions occurs as a result of heating the semiconductor topography. The junctions thus may be partially consumed, ensuring that a low resistance pathway is formed between the salicide and the junctions. Advantageously, the remaining portions of the junctions are sufficiently large to prevent junction spiking entirely through the junctions to the bulk substrate underlying the junctions. In fact, so little of the junctions are consumed during salicide formation that the junction depth may be minimized without suffering increased junction leakage due to junction spiking.

Silicon implantation into selective areas of a refractory metal to

A semiconductor wafer incorporating process control monitors and a method of incorporating the same are provided. In one aspect, the semiconductor wafer has a plurality of fields formed in a pattern thereon that is subdivided into n zones and has a center point. The semiconductor wafer is provided with a plurality of integrated circuits each of which is positioned in one of the plurality of fields. The semiconductor wafer also includes a plurality of diagnostic integrated circuits dispersed in a pattern. The pattern is such that each of the plurality of diagnostic integrated circuits is positioned in one of the plurality fields, one of the plurality of diagnostic integrated circuits is positioned in each of the n zones, and a circle of radius R from the center point will intersect at least one of the plurality of diagnostic integrated circuits where R is greater than or equal to the distance between the center point and the innermost of the plurality of diagnostic integrated circuits and less than or equal to the distance between the center point and the outermost of the plurality of diagnostic integrated circuits.

Useable drop-in strategy for correct electrical analysis of

A combination of optimized layouts using a defect voting technique and the etched quartz approach is used to obtain a high probability of obtaining defect-free printing masks, or reticles 10. The defect voting technique as used herein refers to a technique whereby multiple patterns are overlaid in such a way as to get a partial etch each time. Voting the phase shifter layers reduces the probability of defect printability from the reticle onto a semiconductor wafer. Modeling, using SPLAT, shows the effect of the phase transitions on defect printability, along with the probability of defects 16, 20, 24 printing using the voting technique. Thus, while the mask may not be free of defects, these defects do not print on the wafer.

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Martindale, TX, United States of America

John Lee Nistler