Applied Materials, Inc.

Semitool, Inc.

Varian Semiconductor Equipment Associates, Inc.

John Lee Klocke

Kyle Moran Hanson

Eric J Bergman

Paul R McHugh

Gregory J Wilson

Robert W Batz, Jr

Rajesh Baskaran

Nolan Layne Zimmerman

Bioh Kim

Linlin Chen

John M Pedersen

Marvin L Bernt

Tom L Ritzdorf

Paul Van Valkenburg

Adam Marc McClure

Deepak Saagar Kalaikadal

Jing Xu

Mikael R Borjesson

Kwan Wook Roh

Charles Sharbono

Stuart Crane

Michael Windham

Prayudi Lianto

Richard W Plavidal

Daniel J Woodruff

Arvind Sundarrajan

Kwangduk Douglas Lee

Guan Huei See

Thomas Lee Ritzdorf

You Wang

Terrance Y Lee

Rajesh Prasad

Kyu-Ha Shim

Jason A Rye

Harry S Whitesell

Daniel L Durado

Sam Lee

Robert Douglas Mikkola

Tzu-Yu Liu

Mohamed Rafi

Keith Edward Ypma

Benjamin Clay Bradley

Ning Zhan

Kuma Hsiung

Muhammad Azim

Klaus H Pfeifer

Matthew Herset

John Igo

James Jay Tripp

Carl Campbell Stringer

Aaron Paul Juntunen

James Cournoyer

Method and systems for cleaning and wetting a semiconductor substrate, are provided. Methods and systems include forming an atmosphere in a basin housing the semiconductor substrate with a gas having a higher solubility in a wetting agent than oxygen. Methods and systems include spraying the wetting agent with a spray head onto the substrate while maintaining the atmosphere. Methods and systems include rotationally translating the semiconductor substrate, the spray head, or both the semiconductor substrate and the spray head, Methods and systems include wetting a plurality of features defined in the substrate.

Electroplating wetting chamber with reduced bubble entrapment

Exemplary methods of electroplating include contacting a patterned substrate with a plating bath in an electroplating chamber, where the pattern substrate includes at least one opening having a bottom surface and one or more sidewall surfaces. The methods may further include forming a nanotwin-containing metal material in the at least one opening. The metal material may be formed by two or more cycles that include delivering a forward current from a power supply through the plating bath of the electroplating chamber for a first period of time, plating a first amount of the metal on the bottom surface of the opening on the patterned substrate and a second amount of the metal on the sidewall surfaces of the opening, and delivering a reverse current from the power supply through the plating bath of the electroplating chamber to remove some of the metal plated in the opening on the patterned substrate.

Electrochemical depositions of nanotwin copper materials

Exemplary electroplating systems may include a vessel. The systems may include a paddle disposed within the vessel. The paddle may be characterized by a first surface and a second surface. The first surface of the paddle may be include a plurality of ribs that extend upward from the first surface. The plurality of ribs may be arranged in a generally parallel manner about the first surface. The paddle may define a plurality of apertures through a thickness of the paddle. Each of the plurality of apertures may have a diameter of less than about 5 mm. The paddle may have an open area of less than about 15%.

Electroplating co-planarity improvement by die shielding

The present technology includes methods for rinsing an electroplating apparatus, a component thereof, and/or a substrate. The method includes removing at least a portion of a bath solution having a first pH from an electroplating bath. The method includes filtering the removed bath solution through a nanofiltration membrane, forming a permeating containing a recycled rinse agent, and a retentate. The method includes transferring the recycled rinse agent to the one or more nozzles and rinsing the electroplating apparatus, component thereof, and/or substrate. The method includes where the recycled rinse agent is characterized by a second pH, where the second pH varies from the first pH by less than or about 5.

Nanofiltration for wafer rinsing

A semiconductor processing chamber may process wafers by submerging the wafers in a liquid. To determine when the liquid is free of disturbances or contaminants and thus ready to receive the next wafer, a camera may be positioned to capture images of the liquid after a wafer has been removed from the liquid. A controller may provide the images of the liquid to a neural network to determine when the liquid is ready based on an output of the neural network. The neural network may be trained to identify disturbances, such as ripples, bubbles, or contaminants in the liquid. The controller may then begin controlling the next semiconductor process and submerge the next wafer.

Wafer immersion in semiconductor processing chambers

A method of plating substrates may include placing a substrate in a plating chamber comprising a liquid, and applying a current to the liquid in the plating chamber to deposit a metal on exposed portions of the substrate, where the current may include alternating cycles of a forward plating current and a reverse deplating current. To determine the current characteristics, a model of a substrate may be simulated during the plating process to generate data points that relate characteristics of the plating process and a pattern on the substrate to a range nonuniformity of material formed on the substrate during the plating process. Using information from the data points, values for the forward and reverse currents may be derived and provided to the plating chamber to execute the plating process.

Plating and deplating currents for material co-planarity in semiconductor plating processes

A system may include a first semiconductor processing station configured to deposit a material on a first semiconductor wafer, a second semiconductor processing station configured perform measurements indicative of a thickness of the material after the material has been deposited on the first semiconductor wafer, and a controller. The controller may be configured to receive the measurements from the second station; provide an input based on the measurements to a trained model that is configured to generate an output that adjusts an operating parameter of the first station such that the thickness of the material is closer to a target thickness; and causing the first station to deposit the material on a second wafer using the operating parameter as adjusted by the output.

Parameter adjustment model for semiconductor processing chambers

An electroplating system has a vessel assembly holding an electrolyte. A weir thief electrode assembly in the vessel assembly includes a plenum inside of a weir frame. The plenum divided into at least a first, a second and a third virtual thief electrode segment. A plurality of spaced apart openings through the weir frame lead out of the plenum. A weir ring is attached to the weir frame and guides flow of current during electroplating. The electroplating system provides process determined radial and circumferential current density control and does not require changing hardware components during set up.

Electroplating system

Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

Nanotwin copper materials in semiconductor devices

Exemplary methods of plating are described. The methods may include contacting a patterned substrate with a plating bath in a plating chamber. The patterned substrate includes at least one metal interconnect with a contact surface that is exposed to the plating bath. The metal interconnect is made of a first metal characterized by a first reduction potential. The methods further include plating a diffusion layer on the contact surface of the metal interconnect. The diffusion layer is made of a second metal characterized by a second reduction potential that is larger than the first reduction potential of the first metal in the metal interconnects. The plating bath also includes one or more ions of the second metal and a grain refining compound that reduces the formation of pinhole defects in the diffusion layer.

Diffusion layers in metal interconnects

Electroplating systems according to the present technology may include a two-bath electroplating chamber including a separator configured to provide fluid separation between a first bath configured to maintain a catholyte during operation and a second bath configured to maintain an anolyte during operation. The electroplating systems may include a catholyte tank and an anolyte tank fluidly coupled with the two baths of the two-bath electroplating chamber. The electroplating systems may include a first pump configured to provide catholyte from the catholyte tank to the first bath. The electroplating systems may include a second pump configured to provide anolyte from the anolyte tank to the second bath. The electroplating systems may also include an oxygen-delivery apparatus configured to provide an oxygen-containing fluid within the electroplating system.

Systems and methods for copper (I) suppression in electrochemical deposition

Methods of drying a semiconductor substrate may include applying a drying agent to a semiconductor substrate, where the drying agent wets the semiconductor substrate. The methods may include heating a chamber housing the semiconductor substrate to a temperature above an atmospheric pressure boiling point of the drying agent until a vapor-liquid equilibrium of the drying agent within the chamber has been reached. The methods may further include venting the chamber, where the venting vaporizes the liquid phase of the drying agent from the semiconductor substrate.

Drying high aspect ratio features

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Kalispell, MT, United States of America

John Lee Klocke