Other

Harris Corporation

Intersil Corporation

John Lawrence Benjamin

John M Neilson

Christopher L Rexer

Louise E Skurkey

Linda Susan Brush

Richard Douglas Stokes

Christopher Boguslaw Kocon

Anup Bhalla

Frank Stensney

Christopher Boguslow Kocon

Christopher Michael Scarba

Maxime Zafrani

John Manning Neilson

Christopher Lawrence Rexer

Louis Ellen Skurkey

A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.

Method of making a MOS-gated semiconductor device with a single diffusion

A method of controlling minority carrier lifetime in a semiconductor device in which the density of recombination centers is controlled so that the recombination centers are concentrated in a thin buffer layer adjacent a blocking layer in one of two bonded wafers. The density is controlled by misaligning crystal axes of the two wafers or by doping the bonding surface of one of the wafers before the wafers are bonded. Both methods generate recombination centers in the thin buffer layer that forms around or adjacent the bonding interface. A semiconductor device made by this method includes a buffer layer with a significantly higher density of recombination centers than the adjacent blocking layer to thereby improve control of minority carrier lifetime.

Lifetime control for semiconductor devices

A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.

Method of making MOS-gated semiconductor devices

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Mountaintop, PA, United States of America

John Lawrence Benjamin