Cadence Design Systems, Inc.

John Laurence Rose

Hemant Gupta

Anupam Singal

Praveen Kumar Chhabra

Matthew Aaron Graham

Sharad Gaur

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test ('DUT') and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.

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Longmont, CO, United States of America

John Laurence Rose