Cirrus Logic Inc.

Wolfson Microelectronics Limited

Cirrus Logic International Semiconductor Limited

Seagate Technology Incorporated

John Laurence Pennock

John Paul Lesso

Peter John Frith

Robert David Rand

Colin Steele

Robert James Hatfield

Jean Pierre Lasseuguette

Patrick E Richard

Tsjerk Hans Hoekstra

John Bruce Bowlerwell

David Patten

James Thomas Deas

Gordon Richard McLeod

David Dearn

Mark Hesketh

Santosh Astgimath

Edward M Granville

Sunil Saunders

Mark Jacob

Peter J Firth

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit () includes a first MOS device () and a bias controller (). The circuit is operable in at least a first circuit state (P) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V, V) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Control of semiconductor devices

This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

Data transfer

A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

Charge pump circuit

A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/&#x2212;3VV, +/&#x2212;VV/5 or +/&#x2212;VV/6.

A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

Amplifier circuit and methods of operation thereof

This application relates to computing circuitry (), in particular for analogue computing circuitry suitable for neuromorphic computing. The circuitry () has a plurality of memory cells (), each memory cell having an input electrode () for receiving a cell input signal and an output () for outputting a cell output signal (I, I), with first and second paths connecting the input electrode to the output. The cell output signal thus depends on a differential current between the first and second paths due to the cell input signal. Each memory cell also comprises at least one programmable-resistance memory element () in each of the first and second paths and is controllable, by selective programming of the programmable-resistance memory elements, to store a data digit that can take any of at least three different values. The plurality of memory cells are configured into one or more sets () of memory cells and a combiner module () receives the cell output signals from each of the memory cells in at least one set, and combines the cell output signals with a different scaling factor applied to each of the cell output signals.

Computing circuitry

Embodiments of the present disclosure relate to methods and apparatus for peripheral device discovery, the detection of orientation of a connector having multiple degrees of rotational symmetry, and the provision of appropriate signal paths between a host device and a peripheral device. Some embodiments provide a characteristic impedance within the peripheral device that is coupled between rotationally symmetric contacts of the connector and thus enables detection of the connector orientation. The value of the characteristic impedance may be used in some embodiments to determine the type or model of peripheral device. Some embodiments are concerned with the enablement of appropriate signal paths to a peripheral device having a transducer (e.g. a loudspeaker) coupled only to rotationally symmetric contacts of the connector, such as headphones implemented in a 'balanced' configuration.

Connectors for data transfer

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Midlothian, United Kingdom

John Laurence Pennock