Multigig, Inc.

Other

Analog Devices,inc.

New Transducers Limited

John L Wood

John D Little

Lorianne C Little

Haris Basit

Ryan Jacob Lashlee

Edward Jacob Lashlee

Haris Fozan Basit

Power semiconductor devices can often be expensive to produce and/or expensive to operate (i.e. inefficient). The present structure seeks to overcome these problems by providing a double-sided vertical power transistor structure that poses a unipolar path and a second parallel bipolar path.

Double-sided vertical power transistor structure

Rectifiers are used in power systems, but surges are commonly encountered in the power grid, which can damage switches used to drive the active rectifiers. An active rectification system is proposed in which a 'thyristor' type path is enabled through a transistor device such that surges bypass the driving switches.

Bidirectional bipolar-mode JFET driver circuitry

Double sided versions of several power transistor types are devices that are already known in the literature. Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off condition&#x2014;and a single integrated circuit cannot generally sustain this within a single package. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters. However, problems arising when using a P-type wafer. The present invention seeks to avoid the use of P-type wafers while still getting the higher conduction performance of NPN operation.

We disclose herein a power coupler for connecting AC or DC electrical circuits having different voltages, current or impedance levels. The power coupler comprise a first switching device; a second switching device coupled with the first switching device; a power transformer comprising a first core winding and a second core winding; a first capacitance coupled between the terminals of the first core winding; a second capacitance coupled between the terminals of the second core winding; and a third capacitance coupled between the first and second cores windings. The power transformer is coupled with the first and second switching devices. The power coupler is configured to reduce switching power loss using an adiabatic technique and by selecting appropriate switching time of the switching devices.

Power coupler

A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.

Anodic etching of substrates

We disclose a bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.

Bipolar junction transistor structure

Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Electronic circuitry

Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation.

Electronic pulse generator and oscillator

Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter.

True time delay phase array radar using rotary clocks and electronic delay lines

A multiphase oscillator with a control path for urging the rotational direction of the oscillator is disclosed. The multiphase oscillator has an electrically or magnetically or both continuous signal path over which a signal propagates subject to a phase reversal on each traversal of the signal path and active switching means that create and sustain the propagating signal. A control path has a control signal whose propagation activates each switching means in the order of the direction of propagation of the control signal on the control path so as to determine direction of the signal propagating on the signal path.

System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO.

Dual PLL loop for phase noise filtering

A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprise steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay at target operating frequency. The dividing perimeters of each said region are then divided into segments suitable for approximating lumped transmission-line LKR and relevant parameters determined so that time delays over each such segment are substantially equal to cycle time of desired frequency divided by twice the number of segments. The capacitance of each segment is determined to be substantially equal to the largest envisaged load capacitance (including or preferably differential load capacitance) plus loop-to-loop interconnect capacitance plus active device (say and usually transistor) capacitance of voltage-transition regenerative means and addition to unloaded segments of padding capacitance calculated substantially to match the lumped line capacitance, and pitch/width of differential transmission-line conductors is calculated using Wheeler's formula constrained by metallization factor involved. Finally a suitable odd number of cross-overs of transmission-line conductors is ascertained to meet cross-talk desiderata and number of transmission line loops specified to cover the area to be serviced and their interconnections, say conveniently at corners of rectangular said regions; and account taken of up to all of interconnect inductance, conduction skin effects, cross-talk, and MOSFET parasitics at least for high frequency applications.

Timing circuit CAD

A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results.

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Trabuco Canyon, CA, United States of America

John L Wood