Intel Corporation

Etec Systems, Inc.

Ateq Corporation

John L Wipfli

Robin Lynn Teitzel

Craig B Peterson

Matthew J Jolley

William L Bain, Jr

Gurbir Singh

George W Cox

Robert C Duzett

Allan L Goodman

Morris H Green

David G Carson

James Bruce Campbell

Brad W Hosler

Justin R Rattner

Scott A Ogilvie

Robert C Bedichek

Richard K George

Gerhard Grassl

Artur H Lederhofer

Marcos De Oliveira Camargo

A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8.times.8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e.g., type of object orientation, etc.) into accessing data with the WE generator being driven through a ROM.

Rasterizer for pattern generator

A rasterizer for generating pixel values for a pattern generation apparatus. The pixel values drive the printing mechanism of the pattern generation apparatus. The rasterizer receives a file defining the pattern to be printed, fractures the pattern into sub frames, rasterizes each sub frame and then coordinates the provision of the shaded pixel values to the pattern generation apparatus. The rasterizer of the present invention is comprised primarily of a host processing means for fracturing and translating the file into one or more sub frames of pixels; geometry engines for rasterizing each sub frame; beam boards for providing the pixel shading values to a pattern generation system; a serial bus for coupling the host processor means to the geometry engines and beam boards and a pixel bus for coupling each of the geometry engines to each of the beam boards.

Rasterizer for a pattern generation apparatus

An I/O processor includes an execution unit (EU), a register file, an I/O bus sequencer and a local bus sequencer. The EU decodes an ACCESS instruction having a pointer to a parameter register comprised of: a number of fields for storing a sequencer code identifying one of the sequencers; a logical byte specifying a location in memory to be addressed and valid and block bits; a reply register set pointer to a register set in the register file designated to receive a reply to the ACCESS instruction; and, a length field specifying the location and length of a data block in the register file from which data is to be obtained. A data pointer is generated by taking the logical byte in the parameter register and passing it through a register set mapper to produce a register file physical address. The valid bit of the logical byte is turned off as it is translated by the register the mapper so that the bus sequencer can take control over the corresponding register set. The block bit is set upon the condition that the ACCESS instruction attempts to access a register set whose valid bit is not set, and the block bit is reset upon the condition that the task which is executing the ACCESS instruction attempts to access a register set whose block and valid bits are set.

Multi-tasking register set mapping system which changes a register set

An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.

Memory-based interagent communication mechanism

An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.

Programmable I/O sequencer for use in an I/O processor

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Hillsboro, OR, United States of America

John L Wipfli