Texas Instruments Corporation

John L Wallberg

Robert Bogdan Staszewski

Khurram Waheed

Sudheer Kumar Vemulapalli

Dirk Leipold

Bryan E Bloodworth

Shawn Anthony Fahrenbruch

Vanessa Marie Bodrero

Andrija Jezdic

Prasant K Vallur

An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (K) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (&#x394;f) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (), and the resultant dithered portion (d) can then be applied to a control input of switchable devices within the digitally controlled oscillator.

All-digital frequency synthesis with DCO gain calculation

An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.

Digital phase locked loop with integer channel mitigation

An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.

Interpolative all-digital phase locked loop

A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

All digital phase locked loop architecture for low power cellular applications

An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha&#x2014;&#x3b1;) and an integral loop gain control having a programmable loop gain coefficient (rho&#x2014;&#x3c1;). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.

Digital phase locked loop with gear shifting

A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.

Apparatus and method for acquisition and tracking bank cooperation in a digitally controlled oscillator

A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can be increased to widen the bandwidth of the loop and can also be decreased to narrow the loop bandwidth. The mechanism incorporates an &#x3b1; gear shift circuit, a &#x3c1; gear shift circuit and an optional IIR gear shift circuit. The &#x3b1; gear shift circuit comprises a infinite impulse response (IIR) filtering which enables hitless operation of the PLL loop at the occurrence of gear shift events. The &#x3b1; gear shift circuit comprises an accumulator whose output is multiplied by the gain value &#x3c1;. The invention enables multiple gear shifts in either positive or negative direction to be achieved by configuring the loop gain variables &#x3b1; and &#x3c1; which may be accomplished in software.

Continuous reversible gear shifting mechanism

A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.

Gain normalization of a digitally controlled oscillator in an all digital phase locked loop based transmitter

A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time. This permits the measurement of significantly higher frequency deviations due to the larger capacitances associated with an entire row of capacitors being tested.

Built-in self test method for a digitally controlled crystal oscillator

A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

Circuit for high-resolution phase detection in a digital RF processor

A circuit is designed with a register circuit ( ) arranged to store a control word. A voltage-controlled oscillator ( ) is coupled to receive the control word ( ) and produce a clock signal ( ) having a current frequency corresponding to the control word. A phase detector circuit ( ) is coupled to receive a reference signal ( ) and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector circuit produces a phase signal ( ) having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit ( ) is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word ( ) corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.

Digital phase-locked loop with phase optimal frequency estimation

Fixed gain amplifiers have particular use in the read channel of hard disk drives. A CMOS fixed gain amplifier c having a constant gain over the large dynamic range of hard disk drive applications is provided by incorporating super follower transistors M and M into the input stage of the fixed gain amplifier. The super follower transistors are folded into the output stage of the amplifier. The differential current through the degeneration resistor RE travels through the super follower transistors M and M and into the current mirrors I and I Thus the ac differential current goes directly to the cascoded stage, into the load resistors RL and RL and to the output load.

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Dallas, TX, United States of America

John L Wallberg