Raytheon Company

Santa Barbara Research Center

John L Vampola

Micky R Harris

Bryan W Kean

Sean P Kilcoyne

Steven Botts

Mary J Hewitt

Richard J Peralta

Matthew D Chambers

Kenton T Veeder

Joshua J Cantrell

George Paloczi

Leonard P Chen

John J Drab

Adam M Kennedy

Christian M Boemler

George Grama

Eric R Miller

Richard H Wyles

Jamal I Mustafa

William H Frye

Jehyuk Rhee

Alan W Hoffman

Chad W Fulk

Kevin L Pettijohn

Robert E Eck

Robert C Anderson

Christopher Lynn Mears

Neil R Malone

Richard E Wahl

David A Buell

Andrew E Gin

Roya Mokhtari

Eileen M Herrin

Howard T Chang

Christopher L Mears

Christopher A Hougen

Steven E Botts

Michael McLaughlin

Walter C Trautfield

Robert E Mills

Barry M Starr

Micky Harris

A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Integrating optical elements with electro-optical sensors via direct-bond hybridization

A device includes multiple row power lines and multiple row control lines arranged in rows, where each row control line corresponds to one of the row power lines. The device also includes multiple column power lines arranged in columns. The device further includes multiple unit cells, where each unit cell is coupled to one of the row power lines and one of the row control lines and selectively coupled to one of the column power lines. In addition, the device includes multiple row power switches and multiple column power switches arranged in pairs, where each pair includes one of the row power switches and one of the column power switches. Each pair is configured to selectively (i) connect a corresponding one of the rows and a corresponding one of the columns or (ii) isolate the corresponding one row and the corresponding one column from each other.

Switch-based grid for resiliency and yield improvement

A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

Programmable digital TDI EO/IR scanning focal plane array with multiple selectable TDI sub-banks

An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

Single phase analog counter for a digital pixel

An image capturing device is provided, which includes a capacitive trans-impedance amplifier (CTIA) unit cell. The CTIA unit cell includes an image detector and a switching network. The image detector is configured to detect light having a first color and light having a second color different from the first color, and to generate a photocurrent in response to detecting the light. The switching network includes a CTIA switch, a CTIA low reset switch, and a CTIA high-reset biasing switch. The CTIA switch sets a first reset level of the CTIA unit cell to a first voltage in response invoking a first switching state of the CTIA low-reset switch and sets a second reset level of the CTIA to a second voltage greater than the first voltage level in response to invoking a second switching state of the CTIA low-reset switch.

Single-ended capacitive trans-impedance amplifier (CTIA) unit cell for two-color applications

A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

Digital pixel having high sensitivity and dynamic range

An imaging system includes a focal plane array comprising a first row of photodetectors, a second row of photodetectors adjacent to the first row of photodetectors, and a segmented isolation grid including portions disposed between photodetectors in the first row of photodetectors and photodetectors in the second row of photodetectors.

Segmented channel stop grid for crosstalk mitigation in visible imaging arrays

Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.

Hybrid sensor chip assembly and method for reducing radiative transfer between a detector and read-out integrated circuit

A system including a detector array configured to receive electromagnetic (EM) radiation from a target object, the detector array having one or more detectors is disclosed. The system also includes a readout integrated circuit and one or more processors. The readout integrated circuit has a circuit comprising a number of detector boundary selection components, each one of the number of detector boundary selection components configured to select or adjust a detector boundary from least one of a sub-column boundary or an adjustable boundary.

Detector arrays with electronically adjustable detector positions

According to one aspect, embodiments herein provide a unit cell circuit comprising a photodetector configured to generate a photo-current in response to receiving light, a first integration capacitor configured to accumulate charge corresponding to the photo-current, a second integration capacitor configured to accumulate charge corresponding to the photo-current, a charge diverting switch coupled to the photodetector and configured to selectively couple the first integration capacitor to the second integration capacitor and divert the photo-current to the second integration capacitor in response to a voltage across the first integration capacitor exceeding a threshold level, and read-out circuitry coupled to the first integration capacitor and the charge diverting switch and configured to read-out a first voltage sample from the first integration capacitor corresponding to charge accumulated on the first integration capacitor and to read-out a second voltage sample from the second integration capacitor corresponding to charge accumulated on the second integration capacitor.

Extended high dynamic range direct injection circuit for imaging applications

According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.

Method and apparatus for increasing pixel sensitivity and dynamic range

A combined scanning and staring (SCARING) focal plane array (FPA) imaging system having a plurality of modes of operation is provided. In one example, the SCARING FPA system includes a photodetector array with a plurality of photodetectors arranged in a plurality of photodetector rows, a readout integrated circuit (ROIC) coupled to the photodetector array, and a processor coupled to the ROIC. The processor coupled to the ROIC is configured to dynamically configure the SCARING FPA between a scanning mode of operation and a staring mode of operation.

Systems and methods for combined staring and scanning focal plane arrays

Growing community of inventors

Santa Barbara, CA, United States of America

John L Vampola