Ab Initio Technology LLC

Silicon Graphics, Incorporated

Other

John L Richardson

Marshall Alan Isman

Andrew Fiske Roberts

Richard Alan Epstein

John Ralston

Justin Pniower

Ralf Haug

Paul Bay

Ephraim Meriwether Vishniac

H Mark Bromley

Luis F Stevens

William L Proctor

Glen J Culler

Michael McCammon

Robert B Pearson

Marshall A Isman

A computer-implemented method includes accessing a plurality of data records, each data record having a plurality of data fields. The method further includes analyzing values for one or more of the data fields for at least some of the plurality of data records and generating a profile of the plurality of data records based on the analyzing. The method further includes formulating at least one subsetting rule based on the profile; and selecting a subset of data records from the plurality of data records based on the at least one subsetting rule.

Data records selection

A method for managing data includes receiving individually accessible data units, each identified by a key value; storing a plurality of blocks of data, each of at least some of the blocks being generated by combining a plurality of the data units; and providing an index that includes an entry for each of the blocks. One or more of the entries enable location, based on a provided key value, of a block that includes data units corresponding to a range of key values that includes the provided key value.

Managing storage of individually accessible data units

A method, system, and computer program product for allocating physical memory in a distributed shared memory (DSM) network is provided. Global geometry data is stored that defines a global geometry of nodes in the DSM network. The global geometry data includes node-node distance data and node-resource affinity data. The node-node distance data defines network distances between the nodes for the global geometry of the DSM network. The node-resource affinity data defines resources associated with the nodes in the global geometry of the DSM network. A physical memory allocator searches for a set of nodes in the DSM network that fulfills a memory configuration request based on the global geometry data. The memory configuration request can have parameters that define at least one of a requested geometry, memory amount, and resource affinity. The physical memory allocator in an operating system searches the global geometry data for a set of the nodes within the DSM network that fulfill the memory configuration request and minimize network latency and/or bandwidth. During the search, each node can be evaluated to ensure that the node has sufficient available memory amount and resource affinity. The physical memory allocator can begin a search at locations which are determined based on CPU load, actual memory usage or pseudo-randomly. Faster search algorithms can be used by approximating the DSM network by Boolean cubes.

Method, system, and computer program product for allocating physical memory in a distributed shared memory network

A method, system, and computer program product are provided for profiling virtual memory accesses by one or more threads. A virtual memory access thread profiling tool includes a histogram generator and a thread placement file generator. The histogram generator generates a histogram that indicates the relative frequency at which virtual memory addresses are accessed by each program thread. To generate the histogram, the histogram generator runs and interrupts each program thread to collect samples. When an interrupt is issued, a program counter is returned. A valid load or store instruction is determined for a thread in assembly code identified by the returned program counter. In one example, to determine a valid load or store instruction, the histogram generator walks forward or backward through the assembly code identified by the returned program counter until a valid load or store instruction is reached. A virtual memory address corresponding to a valid load or store instruction is then read. A histogram is then incremented based on the virtual memory address to track the relative frequency at which virtual memory addresses are accessed by each thread. Further options are provided to allow a user to control the virtual memory access profiling tool. These options include selecting and setting the type of collection method, selecting and setting program counter (PC) and memory address filtering, setting the sampling granularity, providing start/stop control, selecting real-time graphical histogram output, and naming output files. The virtual memory access thread profiling tool can be implemented as a profiling command executed by an operating system for a multi-processor system, such as, a NUMA machine.

Method, system and computer program product for profiling thread virtual

An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the functional units. An instruction address register contains instruction addresses for selected locations in the memory having instruction segments stored therein. A memory address circuit reads out an instruction stream comprising instruction segments from the memory in response to the stored instruction address and stores the same in an instruction buffer register. A rotating network, which is operatively coupled to the instruction buffer register, rotates the instruction stream so as to position a selected instruction segment at a predetermined location in a rotating network. A control circuit determines whether the rotating network is required to rotate the instruction stream and, if so, directs the rotating network to position the selected instruction segment at the predetermined location in the rotating network. A first decoding circuit receives and decodes the selected instruction segment to produce a first control signal. A shifting circuit receives the rotated instruction stream and shifts the same an amount equal to at least the width of the selected instruction segment and then applies the same to a second decoding circuit which produces a second control signal. The first and second control signals are adapted to be applied to and commence operation of the functional units in parallel.

Instruction sequencer for parallel operation of functional units

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Santa Barbara, CA, United States of America

John L Richardson