Analog Devices Global

Analog Devices,inc.

Analog Devices Global Hamilton

John L Redford

Michael G Perkins

Boris Lerner

Kaushal Sanghai

Michael S Allen

Andrew James Higham

In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.

Paralleizing loops in the presence of possible memory aliases

In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.

Cache way prediction

According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Predicate counter

The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.

Memory interconnect network architecture for vector processor

Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of 'hits' to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value.

Parallel atomic increment

According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

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Arlington, MA, United States of America

John L Redford