Oak Technology, Inc.

Chipwrights Design, Inc.

John L Redford

A method of determining whether datapaths executing in a computer program should execute conditional processing block includes determining whether processor enable (PE) states of all of the datapaths are disabled, and branching around the conditional processing if the PE states of all of the datapaths are disabled. Branching is not performed, even if the PE states of all of the datapaths are disabled, if the program is determined to be deterministic. That determination is made by evaluating the state of a deterministic bit. Instructions are also provided for carrying out the determining and branching operations. The instructions may also be combined with operations that maintain the PE states during conditional processing.

Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic

A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.

Loop handling for single instruction multiple datapath processor architectures

An apparatus and method for processing portions of data words are described. Data words read from or written to memory are temporarily stored in a data register. Each data word is configured to include multiple portions which can be processed separately. For example, each full data word can be 32 bits long and can include four byte-long data portions. The data word is temporarily stored in a data register for processing. An address register associated with the data register temporarily stores an address word associated with the portion of the data word to be processed. The address word includes an address pointer for the portion of the data word as well as a tag. The tag includes information used to extract the portion of the data word from the data word for processing or to insert the portion of the data word into the data word after processing. The information in the tag can include the size of the data word portion being processed and its location within the data word. The tag can also identify the type of data, e.g., signed or unsigned. Thus, each portion of a data word being processed is associated with a tagged pointer to facilitate extracting and inserting the portion out of and into the associated full data word.

Apparatus and method for using tagged pointers for extract, insert and format operations

An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a single instruction stream, multiple data stream (SIMD) system, and the processing elements can be the multiple data paths of the SIMD system. Each processing element or data path is associated with an identifying value which distinguishes it from the other elements. A memory, which can be configured as an interleaved memory including multiple memory banks, stores data accessed by the processing elements. The data can be a table used for table look-ups for such functions as mathematical operations. Also, multiple copies of the table can be stored in multiple respective banks of the memory. An instruction calling for a memory access such as a table look-up is received. The instruction contains address information which can be a starting address of a table in memory. Each processing element generates an address for performing the memory access by combining at least a portion of its identifying value with the address information in the instruction. The generated address is then used to perform the access. Because the address used for the access depends on the processing element performing the access, the number of simultaneous accesses to a single memory address can be controlled and predicted.

Table look-up operation for SIMD processors with interleaved memory systems

A method and apparatus for optimizing the storage of compressed images includes serially storing pixel block data in memory. Fixed memory utilization can be improved for images having pixel blocks of varying information content. A cumulative memory allocation is updated during processing of each pixel block and compared with the current memory requirement. Memory not utilized for earlier processed pixel blocks having low information content can be used to store later processed high information content pixel blocks.

Method and apparatus for optimizing storage of compressed images in memory

A method and apparatus for decoding of two part binary symbols, such as JPEG symbols, is disclosed. The invention takes advantage of the relationship between the Huffman symbol length, the magnitude length, and the overall symbol length so that none of these lengths need to be stored in memory. Using the invention, a Huffman symbol can be detected. Once the symbol is detected, the invention facilitates the determination of the Huffman symbol length, the magnitude length, and the overall symbol length.

Method and apparatus utilizing a simplified content-addressable memory

A method and apparatus for decoding JPEG Huffman symbols is described. A content addressable memory module stores bit patterns representing Huffman symbols that must be decoded in a single decoding cycle. A compare-add module stores bit patterns representing Huffman symbols that can be decoded in following cycles. The content addressable memory module and the compare-add module each compare a Huffman symbol with their stored bit patterns and generate a corresponding bit pattern when a match is found. The method takes advantage of the high speed possible with a content addressable memory and the small size of the compare-add module.

Method and apparatus for decoding JPEG symbols

A method and apparatus for performing matrix multiplication used in image processing is described. A modified Booth encoding method is used to reduce the logic circuitry in processor modules used for calculating forward and inverse discrete cosine transforms. A set of products of image values and matrix coefficients are generated and provided to a set of multiplexers. The multiplexers provide preselected products to a set of accumulators. The accumulators combine the products to generate the set of transform coefficients at the accumulator outputs.

Method and apparatus for determining discrete cosine transforms using

Method and apparatus for optimizing storage of compressed images in

A method and apparatus for performing an add-masked byte operation on a word of digital data comprises a register for receiving the word, a register for receiving a mask byte, and a multiplication module for receiving inputs from the registers. A multiplier multiplies each byte in the word by a corresponding bit in the mask byte to obtain a series of partial products. A multiplexer shifts the partial products until the partial products are disposed in the same register location as the location of the partial product achieved with the least significant byte in the word. An arithmetic logic unit clears certain bits in the partial products and adds the partial products to obtain a sum. The use of an existing multiplier module in an image processing system eliminates the costs involved in providing additional hardware for performing an add-masked byte operation.

Method and apparatus for performing a masked byte addition operation

A microchip has a register file having a plurality of registers and an accumulator register connected in parallel with the register file that allow write operations to be performed concurrently during a single write cycle. Write operations can include write data to be written to a destination register and identification data designating a destination register. Where a first instruction designates a register in a register file and second instruction designates an accumulator register, write data from the first and second instructions can be written concurrently to the register file and the accumulator register during a single write cycle. By providing an accumulator register that is separate from the register file, data directed toward an accumulator register is diverted away from the register file and delays in performing write operations to the register file are reduced.

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Cambridge, MA, United States of America

John L Redford