Rockwell Collins, Inc.

John L Persick

Mark A Kovalan

Douglas Robert Johnson

Bryon L Wiscons

John W Roltgen

Samir S Hemaidan

James J Corcoran

Eric J Danielson

Ronald W Aull

Stephen I Kotalik

Corydon J Carlson

Gregory E Dunn

Cleveland C Gilbert

Shawn M Stanger

A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.

High integrity computing via input synchronization systems and methods

A data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements is disclosed. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The, data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.

Flexible I/O subsystem architecture and associated test capability

A bus system including a bus user apparatus and a method for communicating via the bus system are disclosed. The bus user apparatus includes means for means for selectively coupling a transmitter to the transmission line according to a protocol of the bus system. The bus system provides bi-directional communication over a single transmission line. The transmitter of the transmitting device is coupled to the transmission line during transmission. Upon completion of transmission, the transmitting device sends a permission to transmit signal to the next transmitting device according to the protocol, and decouples its transmitter from the transmission line. The next transmitting device couples its transmitter to the transmission line and begins transmission of data. Multiple bus users, both transmitters and receivers, are accommodated by the bus system, and bi-directional communication is supported. Further, the data transmission rate may be increased by selectively coupling the transmitter of a receiving device to the transmission line to provide a termination impedance on the transmission line. Higher transmission rates may be accommodated without a termination impedance; if necessary, a termination impedance may be applied. If necessary, the output voltage of the transmitter and the sensitivity of the receiver may be adjusted to accommodate the higher transmission rates. The bus system may also accommodate larger sized words. The bus system is compatible with previously existing systems compliant with an ARINC standard while providing increased capability.

Data bus

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Robins, IA, United States of America

John L Persick