Hewlett-packard Company

John L Moll

Theodore I Kamins

Horng-Sen Fu

Soo-Young Oh

Juliana Manoliu

Shih Yuan Wang

Paul V Voorde

Michael R Ty Tan

Paul J Marcoux

Jean-Pierre Colinge

Kent Okasaki

Chi-Hung Hui

Lynn M Roylance

A method of estimating the distributed capacitance of an interconnection line within an integrated circuit. The invention includes a method for estimating distributed capacitance between interconnection lines within an integrated circuit. The integrated circuit is modeled as including a middle plane which is planar and adjacent to a top plane and a bottom plane. Each plane includes a plurality of interconnection lines which are infinite in length and parallel. The interconnection lines of the middle plane are orthogonal to the interconnection lines of the top plane and the interconnection lines of the bottom plane. A ground plane is adjacent and planar to the bottom plane. A first value of capacitance between an interconnection line of the middle plane and an interconnection line of the top plane is estimated ignoring the effects of the bottom plane. A second value of capacitance between the interconnection line of the middle plane and the interconnection line of the top plane is estimated assuming the bottom plane is a solid conductive sheet. An actual value of capacitance between the interconnection line of the middle plane and the interconnection line of the top plane is estimated by interpolating between the first value of capacitance and the second value of capacitance. The invention simplifies the required calculations by breaking a three array structure into two separate two array structures. Similarly, an actual value of capacitance between the interconnection line of the middle plane and the ground plane, an actual value of capacitance between the interconnection line of the middle plane and an interconnection line of the bottom plane, and an actual value of capacitance between two interconnection lines of the middle plane can be estimated.

Distributed capacitance estimations of interconnects within integrated

A double heterostructure step recovery diode having a very fast step transition time and a high output voltage. A highly doped, wide bandgap p-type region; a narrow bandgap intrinsic region; and a highly doped, wide bandgap n-type region define a PIN diode structure. The intrinsic region forms heterojunctions with the p and n regions. Highly doped, narrow bandgap p and n contact regions adjoin the wide bandgap p and n regions, respectively and form heterojunctions therewith. Very thin, highly doped, narrow bandgap p and n regions are located between the intrinsic region and the wide bandgap p and n regions, respectively. Optional graded bandgap p-type and n-type regions are located between the wide and narrow bandgap p and n regions. In one embodiment the diode is embedded in an undoped wide bandgap material. In an alternate version, the intrinsic region is replaced with a lightly-doped p-type charge storage region to reduce the slow tail portion of the step recovery. An electric field, generated by a graded doping level or a graded bandgap structure, also reduces the slow tail.

Double heterostructure step recovery diode with internal drift field

A method for producing buried oxide layers in selected portions of a semiconductor substrate including the steps of applying a patterned mask made from a high-density material over a semiconductor substrate and selectively forming buried oxide layers by oxygen ion implantation. The high-density material of the mask is preferably tungsten, but can also be made from other suitable materials such as silicon nitride. A MOS transistor is made by the process of the present invention by applying the high-density mask material over the gate of the transistor, and forming buried oxide layers by ion implantation beneath only the source region and drain region of the transistor. The completed MOS transistor has the characteristics of reduced drain and source capacitance, reduced leakage, and faster response, but does not suffer from the floating-body effect of MOS transistors made by SOI processes.

Method for making patterned implanted buried oxide transistors and

A method for producing field oxide in a silicon substrate by forming a thin oxide layer over the surface of the substrate, forming a thin nitride layer over the thin oxide layer, forming a thick oxide over the thin nitride layer, forming a thick nitride layer over the thick oxide layer; patterning all four of the layers to espose the surface of the substrate where the field oxide is to be formed; and growing the field oxide. Preferably, before the field oxide is grown, trenches are formed into the substrate so that the upper surfaces of the field oxide are substantially planar with the upper surfaces of the substrate. The thin oxide layer minimizes bird beak formation, and eases the removal of the oxide/nitride/oxide/nitride layers. The resultant structure is both planar and bird's beak-free, and is therefore well suited to producing VLSI components having dimensions less than 0.5 microns.

Method for producing recessed field oxide with improved sidewall

The present invention provides a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired. Regions of the polysilicon which were not oxidized are suitably doped to function as electrical interconnects to the source and drain regions in the substrate and to the gate. In the preferred embodiment, a metallic interconnection is made between the gate and drain or source region with the second level of polysilicon.

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Palo Alto, CA, United States of America

John L Moll