Motorola Corporation

Freescale Semiconductor,inc.

John L Freeman, Jr

Clarence J Tracy

Robert L Duffin

Gordon M Grivna

Syd R Wilson

Robert A Pryor

Raymond J Balda

Robert J Johnsen

Hank Hukyoo Shin

Paul W Sanders

Julio C Costa

Andrew G Nagy

Willis R Goodner

Nirmal David Theodore

Anthony Polito

James D Paulsen

Alan D Wood

Joseph L Petrucci, Jr

G Scot Srodes

Troy E Mackie

A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within the buried strained layer in conjunction with the introduction of hydrogen.

Method for damage avoidance in transferring an ultra-thin layer of crystalline material with high crystalline quality

In a semiconductor manufacturing method, an emitter region () and a base enhancement region () are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device () is formed on a silicon substrate layer () with an epitaxial layer (). Trenches () are cut into the epitaxial layer () and filled with oxide () to provide reduced junction capacitance and reduced base resistance. The emitter region () and the base enhancement region () are simultaneously formed through an anneal process.

Semiconductor device and method of manufacture

A method of manufacturing a semiconductor component includes providing a composite substrate ( ) with a dielectric portion and a semiconductor portion and growing an epitaxial layer ( ) over the composite substrate. The epitaxial layer has a polycrystalline portion ( ) over the dielectric portion of the composite substrate and also has a monocrystalline portion ( ) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.

Method of manufacturing a semiconductor component

A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

Semiconductor device and method of making

A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Structure and method for metallization of semiconductor devices

A planarized multi-layer metal bonding pad. A first metal bonding pad layer (13) that defines a metal bonding pad is provided. A first dielectric layer (14) is provided with a multitude of vias (17) that covers the first metal bonding pad layer (13), thereby exposing portions of the first metal bonding pad layer (13) through the multitude of vias (17) in the first dielectric (14). A second metal bonding pad layer (18) that further defines the metal bonding pad is deposited on the first dielectric layer (14) making electrical contact to the first metal bonding pad layer through the multitude of vias (17). Planarization of the second metal bonding pad layer (18) is achieved by having the second metal bonding pad layer (18) cover the first dielectric layer (14) and making contact through the vias (17).

Planar multi-layer metal bonding pad

A method is provided for planarizing a multi-layer metal bonding pad. A first metal layer (13) is provided. A first dielectric layer (14) is provided with a multitude of vias (17) covering the first metal layer (13), thereby exposing portions of the first metal layer (13) through the multitude of vias (17) in the first dielectric (14). A second metal layer (18) is deposited on the first dielectric layer (14) making electrical contact to the first metal layer through the multitude of vias (17). Planarization of the second metal layer (18) is achieved by having the second metal layer (18) cover the first dielectric layer (14) and making contact through the vias (17).

Method for making a planar multi-layer metal bonding pad

Metal step coverage is improved by utilizing a multiple step metallization process. In the first step, a thick portion of a metal layer is deposited on a semiconductor wafer at a cold temperature. The remaining amount of metal is deposited in a second step as the temperature is ramped up to allow for reflow of the metal layer through grain growth, recrystallization and bulk diffusion. The thick portion of the metal layer deposited at the cold temperature is of adequate thickness so that it remains continuous at the higher temperature and enhances via filling.

Multiple step metallization process

A residue-free plasma etch of high temperature aluminum copper metallization is provided by the use of a single plasma etcher. The metallization layer is covered by a protective oxide layer. This structure is then placed in the single etcher and a vacuum is established. The protective oxide layer is then etched and without breaking the vacuum or removing the structure from the etcher the metal layer is also etched. This results in the etched surface being residue-free.

Growing community of inventors

Mesa, AZ, United States of America

John L Freeman, Jr