Atmel Corporation

Westinghouse Electric Corporation

United States of America As Represented by the Secretary of the Air Force

John L Fagan

Mark Bossard

Daniel Scott Cohen

Philip C Smith

Donald R Lampe

Marvin H White

Daniel Meyer

A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.

Selectable delay pulse generator

Encryption-based design obfuscation for an integrated circuit includes creating multiple functional circuit paths for an integrated circuit design and selecting among the multiple functional circuit paths during scan testing. Encrypting selection data corresponding to an intended function of the integrated circuit design avoids revealing the intended function as a result of the scan testing.

Method and system for encryption-based design obfuscation for an integrated circuit

System and method for combining signals on a differential signal provided over a communication link. In one aspect, a system for providing a differential communication link includes a signal combination circuit that receives a data signal and a clock signal and outputs a modulated differential signal on a differential link, where the modulated differential signal includes a differential data signal having an offset modulated at a frequency of the clock signal. A receiving circuit receives the modulated differential signal and senses and recovers the data signal and the clock signal therefrom.

System and method for combining signals on a differential I/O link

An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.

Reduced voltage pre-charge multiplexer

A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2possible data values for a group of M data bits uniquely corresponds to one of 2distinct pulse widths. This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.

Method for performing dual phase pulse modulation

A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.

Dual phase pulse modulation system

A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.

Vernier circuit for fine control of sample time

An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.

An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.

Dual phase pulse modulation encoder circuit

A memory apparatus having a row and column decoder for controlling the read and write function to a transistor memory pair. A single power/chip select pad is utilized to both power the memory and select the memory chip. External control signals are applied directly to critical internal node within the memory apparatus.

Fast access non-volatile memory

An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

Precharge circuitry for an electrically alterable non-volatile memory

Memory array address buffer with level shifting

Memory using interleaved rows to permit closer spacing

A method and apparatus for charge addressing a non-volatile MNOS memory cell in a LSI array of memory cells, is disclosed. Each MNOS cell of the array is made up of a substrate; adjacent diffusion areas in the substrate; a memory window intermediate the adjacent diffusion areas, controlled by a memory gate; and an enable gate adjacent the memory window and overlapping one of the diffusion areas. The memory gate and the enable gate are each separated from the substrate and each other by silicon dioxide/silicon nitride layers to provide a capacitive dielectric. Addressing of an individual cell in the array is achieved by selective activation of a corresponding enable gate and a corresponding memory gate, which are formed in an orthogonal grid array. The cell is accessed by a single stage of a shift register for both read and write operations through a transfer gating means.

Method and apparatus for addressing a non-volatile memory array

A random access memory cell for storing information in both volatile and nonvolatile form is described incorporating a dual gate variable threshold transistor, a capacitor, and three field effect transistors. The dual gate variable threshold transistor may include a fixed threshold and a variable threshold field effect transistor.

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Pasadena, MD, United States of America

John L Fagan