Broadcom Corporation

John L Creigh

Oscar Ernesto Agazzi

Mehdi Hatamian

Henry Samueli

Arthur Abnous

David E Kruse

Arya Behzad

Ramon Alejandro Gomez

Klaas Bult

Tom W Kwan

Chi-Hung Lin

Scott R Powell

Kevin Brown

Richard G Thousand

Kishore Kota

Kadir Dinc

Mehdi Tavassoli Kilani

Hooman Parizi

Tooraj Esmailian

The present disclosure is directed to a system and method for continually adapting a channel equalizer that includes a precoder based on changing channel conditions. The precoder is described as being implemented in the exemplary context of a 10GBASE-T physical layer (PHY) device. 10GBASE-T is defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3an standard and uses four pairs of copper transmission lines to provide an aggregate data rate of 10 gigabits per second. In this exemplary context, the system and method of the present disclosure are configured to exploit an undefined, auxiliary bit in the 10GBASE-T transmission frame to continually send updates to the coefficients of the precoder based on changing channel conditions. The updates can be sent in the transmission frames together with application-level data.

Continuous adaptation of a channel equalizer

Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Method and system for interference cancellation

The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

Standby mode for use in a device having a multiple channel physical layer

Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Gigabit ethernet transceiver with analog front end

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements

Method and device for multi-dimensional processing using a single-state decision feedback equalizer

A physical coding sublayer (PCS) transmitter circuit generates a plurality of encoded symbols according to a transmission standard. A symbol skewer skews the plurality of encoded symbols within a symbol clock time. A physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals. A PCS receiver encoder generator generates the encoding parameters.

Physical coding sublayer for a multi-pair gigabit transceiver

A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase. The protocol then enters a fourth stage in which the master transceiver and the slave transceiver are ready to communicate with each other.

Startup protocol for high throughput communications systems

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

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Rancho Santa, CA, United States of America

John L Creigh