Fairchild Semiconductor Corporation

John L Benjamin

Joseph Andrew Yedinak

Thomas E Grebs

Mark L Rinehimer

Jifa Hao

Randall L Case

Dean E Probst

Jack H Linn

Gary M Dolny

Rodney S Ridley

Frank Stensney

Jae J Yun

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Reduced process sensitivity of electrode-semiconductor rectifiers

Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.

Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

Trench-shielded semiconductor device

A power semiconductor device having high avalanche capability comprises an Ndoped substrate and, in sequence, Ndoped, Pdoped, and Pdoped semiconductor layers, the Pand Pdoped layers having a combined thickness of about 5 &#x3bc;m to about 12 &#x3bc;m. Recombination centers comprising noble metal impurities are disposed substantially in the Nand Pdoped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an Ndoped epitaxial layer on an Ndoped substrate, forming a Pdoped layer in the Ndoped epitaxial layer, forming a Pdoped layer in the Pdoped layer, and forming in the Pand Ndoped layers recombination centers comprising noble metal impurities. The Pand Pdoped layers have a combined thickness of about 5 &#x3bc;m to about 12 &#x3bc;m.

Power semiconductor device with improved unclamped inductive switching capability and process for forming same

A process for filling a trench having sidewalls and a floor in a semiconductor device or integrated circuit comprises: forming an insulating layer on the sidewalls and floor of a trench in a semiconductor substrate, substantially filling the trench with semiconductor material, removing semiconductor material from an upper portion of the trench, depositing a first layer of BPSG in the upper portion of the trench, heating the substrate to a first temperature greater than about 850&deg; C. and up to about 1100&deg; C., depositing a second layer of BPSG above the first layer of BPSG, and heating the substrate to a second temperature greater than about 850&deg; C. and up to about 1100&deg; C. The first and second BPSG layers each comprises boron and phosphorus in a weight ratio of boron: phosphorus of greater than 1:1.

Process for depositing and planarizing BPSG for dense trench MOSFET application

In an improved process for controlling and improving minority carrier lifetime in a P-i-N diode, platinum is deposited on a surface of a silicon semiconductor substrate containing at least one PN junction. The substrate is heated to a temperature of about 800&deg; C., and the platinum is diffused into the substrate as its temperature is increased at a rate of about 5&deg; C./minute to a first selected temperature of about 850-950&deg; C. Platinum diffusion is continued while the substrate is maintained at the first selected temperature for about 30-60 minutes. The substrate temperature is then increased at a rate of about 5&deg; C./minute to a second selected temperature above 950&deg; C. to about 1000&deg; C., and the substrate is maintained at the second selected temperature for about 5-30 minutes before cooling.

Growing community of inventors

Mountain Top, PA, United States of America

John L Benjamin