Intel Corporation

John L Baudrexl

Vui Yong Liew

David W Grawrock

Huimin Chen

Bruce Querbach

Dave B Minturn

Tieyu Zheng

Ronald W Swartz

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Hermann Gartler

Ashok N Kabadi

Susan S Meredith

Samie B Samaan

Keith A Drescher

Jay Joseph Nejedlo

Mukesh Kataria

Lyle E Cool

David L Chalupsky

James J Grealish

Russell J Wunderlich

Brian Meyer

Abhijit Davare

Keith A Jones

Priyadarsan Patra

William Penner

Ridvan A Sahan

Rahima K Mohammed

Arun R Ramadorai

Kapila B Udawatta

Wee Hoo Cheah

Yuen Tat Lee

Warren R Morrow

Christian E Iovin

Loren James McConnell

Kip C Killpack

Kyle Markley

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Travis K Goff

Evan J Halprin

Jiun Long Foo

Wendell S Wenjen

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

In-band configuration mode

A bus bridging method, a bus bridge and a bus agent are described. In a bus agent provides to a bus bridge a read data request targeting a data source bridged by the bus bridge. The read data request includes a read address indicating a starting storage location of the requested data, and a read size indicator indicating the size of the requested data. The bus bridge, in response, facilitates provision of the requested data to the bus agent. The facilitation includes streaming buffered ones of the requested data to the bus agent through one or more successive streaming connections to the bus bridge by the bus agent.

Bus bridging method and apparatus including use of read size indicators

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Olympia, WA, United States of America

John L Baudrexl