Digital Equipment Corporation

John Kirk

George H Lord

Kenneth Alan House

Kim A Meinerth

Larry Narhi

Lawrence Narhi

A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry into, or displacement from, the CPU cache tag store is also entered into, or displaced from, the second cache tag store. The disclosure further describes a computer graphics system, having a graphics processor capable of reading from or writing to main memory, including virtual memory, without any action by the CPU; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a residue buffer for the temporary storage of memory transmissions not immediately usable by the graphics processor; having a 'short circuit' feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.

Duplicate cache tag store for computer graphics system

A bus interface employs a bus extender for connecting an auxiliary bus to a single port on a main bus in such a way as to interconnect one or more host computers on the main bus to one or more peripheral devices on the auxiliary bus. The bus extender employs a transceiver coupled to the main bus, another coupled to the auxiliary bus, and signal transfer and logic circuitry passing signals between and controlling the operation of the transceivers. The circuitry also performs all address translation necessary for inter-bus communication. Once communication links have been established with the designated devices on the other bus, the extender sends message data signals received over the one bus directly onto the other bus without modification. Since the interface can comply with SCSI standards, any of a variety of types of commercially available peripheral devices having controllers complying with those standards can be supported on the auxiliary bus.

SCSI interface employing bus extender and auxiliary bus

A computer workstation including a processor, one or more input/output units, such as disk devices or network interfaces, a program memory and a video memory which contains video information displayed on a video monitor. An arbitration circuit selects among the processor and input/output units for transfers to and from the program memory and video memory. A master control circuit controls timing of transfers to and from the program and video memories, and periodically enables video update transfers of video information from the video memory to video control circuits, which control the video monitor. While a video update is in progress, the master control circuit holds off other transfer request of the processor and input/output units with the memory. The program memory stores interrupt vectors. In response to interrupt requests from units which require interrupt service, the master control circuit interrupts the processor. When the processor acknowledges the interrupt, the master control circuit enables the transfer from the memory to the processor of the interrupt vector associated with the highest priority interrupt.

Computer workstation including video update arrangement

A bus data path control scheme facilitates communications in a data processing system between subsystem elements that have different data widths. A plurality of buses is provided whereby each subsystem or element is connected to one of the plurality of buses. A control logic array detects requests to transfer data between subsystems. Each of the plurality of buses are connected to one another through a bidirectional transceiver. Once the control logic array detects the request for transferring data between subsystems, the array and the transceiver operate in concert to permit subsystem devices having different data widths to communicate with one another. In particular, the array and transceiver act to redirect data so that as it is shifted from a first bus to which the sending subsystem is connected to a second bus to which the receiving subsystem is connected, the data is moved into the proper bit location on the second bus so as to be received properly by the receiving subsystem.

Growing community of inventors

Boxboro, MA, United States of America

John Kirk