Sharp Kabushiki Kaisha Corporation

John Kevin Twynam

Toshiaki Kinosada

Motoji Yagura

Katsuhiko Kishimoto

Hiroshi Kawamura

Nobuyuki Ito

Yoshiaki Nozaki

Koken Yoshikawa

Norimasa Yafune

Naoki Takahashi

Naoyasu Iketani

Hiroya Sato

Keiichi Sakuno

Yoshiteru Ishimaru

Toshiyuki Shinozaki

Tetsuzo Nagahisa

Masaharu Yamashita

Tomohiro Nozawa

Masatomo Hasegawa

Masanori Kominami

A normally-off-type HFET includes: an undoped AlGaN layer of tthickness, an undoped AlGaN layer of tthickness and an undoped GaN channel layer of tthickness that are sequentially stacked; a source electrode and a drain electrode separated from each other and electrically connected to the channel layer; an undoped AlGaN layer of tthickness formed between the source electrode and the drain electrode on the channel layer; an AlGaN layer of tthickness formed in a shape of a mesa on a partial area of the AlGaN layer between the source electrode and the drain electrode; and a Schottky barrier type gate electrode formed on the AlGaN layer, in which conditions of y&#x3e;x&#x3e;w&#x3e;z, t&#x3e;t&#x3e;tand 2wt/(x&#x2212;w)&#x3e;t&#x3e;1 nm are satisfied.

Normally-off-type heterojunction field-effect transistor

This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.

Composite semiconductor device

One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.

Semiconductor device

A field-effect transistor provided with a substrate, a channel layer, a carrier supply layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer that is laminated on the carrier supply layer between the source electrode and the drain electrode, and suppresses current collapse, an opening that is formed between an edge of the first insulating layer opposing the drain electrode and the drain electrode, and a second insulating layer that is laminated on the carrier supply layer exposed in the opening.

Field-effect transistor

A GaN heterojunction FET has an AlGaN first graded layer and an AlGaN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for example, 0.2 at an interface of the first graded layer with the channel layer to 0.1 at an interface thereof with the second graded layer. The Al mole fraction y of the second graded layer increases from, for example, 0.1 at an interface of the second graded layer with the first graded layer to 0.35 at a surface located on the opposite side from the first graded layer. Because the intrinsic polarization of AlGaN depends on the Al mole fraction, fixed negative charge is generated in the AlGaN first graded layer, and fixed positive charge is generated in the AlGaN second graded layer.

Field effect transistor having recessed gate in compositional graded layer

A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.

Field effect transistor

A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner of the polygon has an interior angle of which an outward extension line of a bisector crosses the semiconductor layer or the second electrode. The interior angle of such a second electrode-side corner is larger than 90&#xb0;.

In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiOlayer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiOof the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.

Electronic device and heterojunction FET

A semiconductor switching element, wherein on a semiconductor layer formed on a substrate, or on a semiconductor substrate, a source electrode and a drain electrode are disposed at a predetermined interval in a direction along a surface of the substrate; and a second gate electrode is provided between the source electrode and the drain electrode, the second gate electrode is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.

Semiconductor switching element and semiconductor circuit apparatus

In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like.

Voltage clamp circuit and semiconductor device, overcurrent protection circuit, voltage measurement probe, voltage measurement device and semiconductor evaluation device respectively using the same

In a heterostructure field effect transistor (MISHFET), a source ohmic electrodeand a drain ohmic electrodeare formed on an AlGaN barrier layerA SiNx gate insulatora p-type polycrystalline SiC layerand a Pt/Au gate electrodebeing an ohmic electrode are formed one on another on the AlGaN barrier layerSince the p-type polycrystalline SiC layeris relatively large in work function, the channel of the MISHFET is depleted even in its zero-bias state, so that the normally-OFF operation occurs.

Insulated-gate field effect transistor

On a substrate of a GaN FET, an undoped AlN layer, a GaN delta doped layer, an undoped GaN layer, and an undoped AlGaN layer are formed in sequence. Arranged on the undoped AlGaN layer are a Ti/Al/Pt/Au source ohmic electrode, a Pt/Au gate Schottky electrode, and a Ti/Al/Pt/Au drain ohmic electrode. Parallel conduction and gate leak are reduced or eliminated by the GaN delta doped layer.

Compound semiconductor FET

A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer is provided on the emitter layer. A p-type carrier retaining layer is formed between the collector layer and the emitter layer. The p-type carrier retaining layer temporarily retains the p-type carriers that are injected from the gate layer into the emitter layer and diffused in the emitter layer and reach the p-type carrier retaining layer. The bipolar transistor has a structure whose performance is not influenced by sheet resistance of the base layer, and is able to exhibit a high current gain even in a high-frequency region.

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Osaka, Japan

John Kevin Twynam