International Business Machines Corporation

Infineon Technologies Ag

Kabushiki Kaisha Toshiba

Headway Technologies, Incorporated

Other

Siemens Aktiengesellschaft

Globalfoundries Inc.

Infineon Technologies North America Corp.

John Kenneth DeBrosse

Daniel Christopher Worledge

Chung H Lam

Janusz Jozef Nowak

Hing Wong

Yutaka Nakamura

Matthew R Wordeman

Jack Allan Mandelman

Toshiaki Kirihata

Gary Bela Bronner

Hillery C Hunter

Jonathan Zanhong Sun

Dietmar Gogl

Chih-Chao Yang

Lawrence Alfred Clevenger

Carl John Radens

Warren Edward Maule

Timothy Joseph Dalton

Kyu-hyoun Kim

Anthony J Annunziata

Michael C Gaidis

Charles Arthur Kilmer

Heinz Hoenigschmid

Thomas M Maffitt

Mark C H Lamorey

Louis L C Hsu

Keith Kwong-Hon Wong

Kotb Jabeur

Rona Yaari

John Edward Cronin

Po-Kang Wang

William Robert Reohr

Yu Lu

Stefan Lammers

Yohji Watanabe

Hans Viehmann

Pouya Hashemi

Lars W Liebmann

Jeffrey A Stuecheli

Wendell P Noble

Chandrasekharan Kothandaraman

David William Abraham

Edmund Juris Sprogis

Todd Edward Takken

Michele M Franceschini

Anthony Richard Bonaccio

William Joseph Gallagher

Kailash Gopalakrishnan

Rainer Leuschner

Russell J Houghton

Ulrike Gruening

Paul Christian Parries

Gerhard Mueller

William Eric Hall

Stuart Stephen Papworth Parkin

Philip Louis Trouilloud

Donald M Kenney

Gerhard Ingmar Meijer

Jing Li

Blake G Fitch

Johannes Georg Bednorz

Hans-Heinrich Viehmann

Scott Josef Bukofsky

Ciaran J Brennan

Rick L Mohler

Jenifer E Lary

Daniel J Nickel

Juergen Preuninger

Dale L Critchlow

Marco Hug

Carl Radens

A spin-orbit torque magnetoresistive random-access memory device formed by forming an array of transistors, where a column of the array includes a source line contacting the source contact of each transistor of the column, forming a spin-orbit-torque (SOT) line contacting the drain contacts of the transistors of the row, and forming an array of unit cells, each unit cell including a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SOT line, where the SOT-MRAM cell stack includes a free layer, a tunnel junction layer, and a reference layer, a diode structure above and in electrical contact with the SOT-MRAM cell stack, an upper electrode disposed above and in electrical contact with the diode structure.

Spin-orbit-torque magnetoresistive random-access memory array

Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.

Dynamic boosting techniques for memory

A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.

Dynamic redundancy for memory

A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blof the second subset of the reference memory bit cells outputs a read reference signal.

Tunable reference system with sense amplifier offset cancellation for magnetic random access memory

A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.

Trimming MRAM sense amp with offset cancellation

A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

Bad bit register for memory

Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.

Magnetic tunnel junction based anti-fuses with cascoded transistors

A method includes applying a first voltage to a source of a first p-channel FET connected in series with a second p-channel FET, applying a second voltage, lower than the first voltage, to a source of a third p-channel FET connected in series with a fourth p-channel FET, applying a third voltage, lower than the first and second voltages, to a source of a second n-channel FET connected in series with a first n-channel FET, drains of the second p-channel FET, the fourth p-channel FET, and the first n-channel FET connect at a connection point including an output terminal for outputting an output signal, and outputting one of the first voltage, the second voltage, and the third voltage from the output terminal based on input signals inputted to corresponding gates of the first p-channel FET, the third p-channel FET, the fourth p-channel FET, and the second n-channel FET.

Dual power rail cascode driver

Improved spin hall MRAM designs are provided that enable writing of all of the bits along a given word line together using a separate spin hall wire for each MTJ. In one aspect, a magnetic memory cell includes: a spin hall wire exclusive to the magnetic memory cell; an MTJ disposed on the spin hall wire, wherein the MTJ includes a fixed magnetic layer separated from a free magnetic layer by a tunnel barrier; and a pair of selection transistors connected to opposite ends of the spin hall wire. An MRAM device and method for operation thereof are also provided.

Three terminal spin hall MRAM

Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.

Secure off-chip MRAM

A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.

Cascode complimentary dual level shifter

According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Adaptive error correction in a memory system

Improved STT MRAM source line configurations are provided. In one aspect, a STT MRAM array includes: a plurality of cells including magnetic tunnel junctions in series with field effect transistors; a plurality of word lines perpendicular to a plurality of bit lines; a plurality of source line segments spanning m+1 of the bit lines, wherein m of the bit lines include regular array bit lines, and wherein at least one other of the bit lines includes an extra bit line that is connected to the source line segments such that the source line segments span the regular array bit lines and the extra bit line. An STT MRAM device and a method for operating an STT MRAM device are also provided.

STT MRAM source line configuration

A bit line clamp voltage generator circuit for a Spin Torque Transfer Magnetoresistive Random Access Memory is provided. The circuit includes a negative channel Field Effects Transistor having a source, a drain, and a gate, the gate being connected to the drain. The circuit further includes a resistor Rs having a first end connected to a first voltage and a second end connected to the source. The circuit also includes a resistor Rd having a first end connected to a second voltage and a second end connected to the drain to form an output node for outputting a bit line clamp voltage.

Bit line clamp voltage generator for STT MRAM sensing

Growing community of inventors

Colchester, VT, United States of America

John Kenneth DeBrosse