Texas Instruments Corporation

John Kenneth Arch

Ye Shao

Thomas Dyer Bonifield

Byron Lovell Williams

Anant Shankar Kamath

Raja Selvaraj

Binghua Hu

Louis N Hutter

John P Erdeljac

Guruvayurappan Mathur

Poornika Fernandes

Paul Stulik

M Ali Khatibzadeh

Taylor R Efland

Xiaoju Wu

Han-Tzong Yuan

Jau-Yuann Yang

Jeffrey P Smith

Xinfen Chen

Qingfeng Wang

C Matthew Thompson

Mary Ann Murphy

A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

Deep trench intersections

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Device isolator with reduced parasitic capacitance

A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.

Deep trench isolation with segmented deep trench

An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

Stacked capacitor

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator

The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure in, on or over a substrate of a semiconductor device, the buried layer test structure including a first test buried layer located in or on the substrate, the first test buried layer shifted a predetermined distance with respect to a first test feature. The buried layer test structure further includes a second test buried layer lodated in the substrate, the second test buried layer shifted a predetermined but different distance with respect to a second test feature. The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure to determine an actual shift relative to the predetermined shift.

Method for detecting epitaxial (EPI) induced buried layer shifts in semiconductor devices

A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Metalization outside protective overcoat for improved capacitors and inductors

A power field effect transistor is disclosed that includes polysilicon gate bodies (,) and (,), which includes platinum silicide contact layers (,) and (,) disposed on the outer surfaces of bodies (,) and (,), respectively. In addition, the device comprises an n&plus;drain region (,) which also has a platinum silicide drain contact layer (,) formed on its outer surface and platinum silicide source contact layers (,) and (,). During formation, sidewall spacers (,) and (,), as well as mask bodies (,) and (,) are used to ensure that platinum silicide layer (,) spaced apart from both gate bodies (,) and (,) and platinum silicide gate contact layers (,) and (,).

Growing community of inventors

Richardson, TX, United States of America

John Kenneth Arch