Micron Technology Incorporated

Intel Corporation

Other

John K Zahurak

Sanh D Tang

Kunal R Parekh

Richard H Lane

Charles H Dennison

Mark Fischer

Gurtej S Sandhu

Jun Liu

Phillip G Wald

David L Dickerson

Haitao Liu

Hongmei Wang

Byron Neville Burgess

Fernando N Gonzalez

Werner Juengling

Randhir P Thakur

Fawad Ahmed

Brent Keeth

Scott E Sills

Randhir P S Thakur

Michael P Violette

Nishant Sinha

Jigish D Trivedi

Klaus Florian Schuegraf

Martin Ceredig Roberts

Thomas M Graettinger

Hong Li

Suraj J Mathew

Lars P Heineck

Silvia Borsari

Wolfgang Mueller

Amirhasan Nourbakhsh

Durai Vishak Nirmal Ramaswamy

Chandra V Mouli

Pierre C Fazan

Roy Edward Meade

Shubneesh Batra

Ming Zhang

David K Hwang

Andrew M Bayless

Xiaonan Chen

Alessandro Torsi

Shane J Trapp

Muralikrishnan Balakrishnan

Jay Parks

Siddartha Kondoju

David H Wells

Krishna Kumar Parat

Thomas Arthur Figura

Bhaskar Srinivasan

Michael L Nuttall

Scott J Deboer

John P Friedenreich

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

Charge storage apparatus and methods

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Three dimensional memory and methods of forming the same

Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies, and methods of forming integrated assemblies

Methods of forming integrated assemblies

Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.

Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures

Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

Memory arrays and methods of forming memory cells

Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Thyristor random access memory device and method

Growing community of inventors

Eagle, ID, United States of America

John K Zahurak