Emc Corporation

John K Walton

Christopher S MacLellan

Kendell Alan Chilton

Daniel Castel

Michael Bermingham

Eli Leshem

James Marriott Guyer

William F Baxter

Gregory S Robidoux

Robert A Thibault

Paul C Wilson

Mark J Halstead

Haim Kopylovitz

Steven T McClure

Brian William Gallagher

Brett D Niver

Ofer Michael

William R Tuccio

Brian K Campbell

Robert DeCrescenzo

Ofer Porat

James M McGillis

Mark Zani

Farouk Khan

Brian D Magnuson

Steven MacArthur

Kendall A Chilton

A method and structure for detecting whether the packets received by the switch are low latency packets or high bandwidth packets and routing detected low latency packets to a first one of a pair of switching structures and for high bandwidth packets to a second one of the pair of switching structures. The switch includes an output section for detecting whether a low latency packet is being received during transmission of a high bandwidth packet and, under such detected condition interrupting the transmission of the high bandwidth packet, transmitting the low latency packet, and then transmitting a remaining portion of the high bandwidth packet. The switch inserts delimiters at the start of transmission of the low latency packet and an end of transmission of the low latency packet. The transmission of the low latency packet commences immediately upon detection of such low latency packet.

Method and system for reducing packet latency in networks with both low latency and high bandwidths requirements

A packet switching network having a plurality of nodes and a network having: a plurality of switches couples to the nodes and links interconnecting ports of the plurality of switches. Each one of the switches has a normal routing table for routing packets from a source one of the nodes to a destination one of the nodes through the network in according to the normal routing table and, for, upon such upon such source one of the nodes detecting a fault in transmission of such packet, routing such to a predetermined designated fault one of the ports of such switch.

Fault isolation and handling in a packet switching network

A system for minimizing power consumption of a multiprocessor data storage system is disclosed. The system utilizes processors that are capable of operating at a number of different reduced power modes, such that the processors operate at full power during peak workloads, but can be powered down during low workload times. When the onset of peak loads are detected through monitoring I/Os per second ('IOPS') and/or response times of the system, the processors are brought out of power-down mode to handle the increased IOPS during the peak loads. In this manner, the majority of the processors only operate at full power when the system experiences peak loads. During normal and low load times, the processors are either operated at reduced power or are powered down. This results in a significant reduction in power consumption of the system.

Method and system for minimizing power consumption in a multiprocessor data storage system

Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.

Method, computer readable medium, and data storage system for selective data replication of cached data

A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

Data system having a virtual queue

A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Data storage system having shared resource

A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.

System having backplane performance capability selection logic

A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.

Data storage system having cache memory manager with packet switching network

In one embodiment, a data storage system is provided may include an input/output (I/O) controller, and first and second memory boards. The controller may receive data and a request to store the data in the system, and may include memory for initially storing the data. The first memory board may store, in response to a first memory storage request, a first copy of the data initially stored in the controller. The first memory board may provide to the controller a first status indication indicating whether the first memory board successfully stored the first copy. The second memory board may store, in response to receipt of a second memory storage request, a second copy of the data. The controller may provide a second status indication, indicating whether the request to store the data in the system was successful.

Method and system for maintaining data integrity using dual write operations

A system wherein data is read from, and store in, a memory, such data having associated therewith an address/control portion. The system includes a pair of controller sections, one of such sections being a primary section and the other one of the sections being a secondary section. Both such sections are configured to implement identical control logic in controlling the transfer of such data between a first port connected to the pair of control sections and a write data port. The write data port of the primary section is connected to the memory. The first port receives an address/control portion associated with the data. A checker is included for producing a no-operation (NOOP) command to the memory if logic signal produced by the pair of control logic from the address/control portion at the first port are different from one another. The memory is configured to inhibit storage of data in the memory at the data port in response to the NOOP command.

Data storage system having no-operation command

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

Data storage system having point-to-point configuration

A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a directors interconnected through an interface state data bus and end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the end-user data buses has a first end coupled to a corresponding one of the directors and a second end coupled to the memory. The directors control the end-user data transfer between the host computer and the bank of disk drives through the memory in response to interface state data generated by the directors as such end-user data passes through the end-user data busses. The generated interface state data is transferred among the directors through the memory as such end-user data passes through the end-user bus.

Data storage system

A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes providing a plurality of successive full adders, each one of the full adders being associated with a corresponding one of the bits of the plural bit read data. Each one of the full adders has a summation output, a carry bit input and a carry bit output. The method includes adding in each one of the full adders: (a) a corresponding bit of plural bit input data provided by the director; (b) the corresponding one of the bits of the plural bit read data; and, (c) a carry bit fed the carry bit input from a preceding full adder. Each one of the full adders provides: (a) a carry bit on the carry output thereof representative of the most significant bit produced by the full adder; and, (b) a bit on the summation output representative of a least significant bit produced by the full adder. The bit on the summation output is stored in a corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, the carry bit produced from one of the full adders to the carry bit input of a next successive full adder selectively in accordance with a corresponding bit of a plural bit carry bit mask provided by the director providing a full adder for each one of the bits of the plural bit read stored. The full adder has a carry bit input and a carry bit output. The method includes adding each one of a bits of plural bit input data provided by the director with a corresponding one of the bits of the plural bit read data in the provided full adder together with a carry bit fed the carry bit input of such provided full adder. The full adder provides: a carry output bit; and, a summation of the bits fed to such provided full adder to the corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, a carry bit produced by one full adder provided for a lower order bit of the plural bit read data to the carry bit input of a second full adder provided by for next, successive higher order bit of the plural bit read data selectively in accordance with one of a plurality of bits of a carry bit mask provided by the director.

Data storage system having atomic memory operation

A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory. The plurality of directors control the end-user data transfer between the host computer and the bank of disk drives through the memory in response to interface state data generated by the directors as such end-user data passes through the end-user data busses. The generated interface state data is transferred among the directors through the memory as such end-user data passes through the end-user bus.

In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.

Growing community of inventors

Mendon, MA, United States of America

John K Walton