Purdue Research Foundation

Other

John K Lynch

Pedro P Irazoqui

Jerry L Wilson

Richard B Ingram

An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.

Memory array with reduced read power requirements and increased capacity

A semiconductor building block is disclosed which includes a plurality of logic gates, each having at least one P-channel device, at least one N-channel device, and a current controller controlling current for each of the plurality of logic gate having a voltage source input (vdd), a ground input (vss), a first input current (ibias) adapted to control current through the at least one N-channel device, a second input current (ibias) adapted to control current through the at least one P-channel device, and an analog voltage input (delta) representing i) a predetermined ratio between respective on currents in the at least one P-channel device to ibias, and ii) the predetermined ratio between respective on currents in the at least one N-channel device to ibias.

Low power logic family

Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines. The indicator has an on and an off condition and a switch is provided for stopping the current in the controlled current source when the indicator is activated in the on condition. The current in the controlled current source is stopped when the voltage change on the read bit line is greater than a predetermined threshold.

Memory architecture with a current controller and reduced power requirements

The PMMA (Polymethyl methacrylate) plastic used to produce one-piece intraocular lenses is modified by a novel thermoplastic pressure forming process to produce a much tougher material with improved mechanical properties. The improved material exhibits greater ductility and fatigue resistance than conventional cast PMMA sheet, resulting in a one-piece lens that is less prone to breakage from implantation or use.

Growing community of inventors

West Lafayette, IN, United States of America

John K Lynch