Micron Technology Incorporated

Micron Display Technology, Inc.

Round Rock Research, LLC

Other

John K Lee

David A Cathey

Behnam Moradi

Luan C Tran

Tianhong Zhang

Kevin W Tjaden

Eric Higgins Freeman

Russell Nielsen

Gurtej S Sandhu

Glen Earl Hush

Zhiping Yin

D Mark Durcan

Mirzafer K Abatchev

Paul A Morgan

James J Hofmann

Shuang Meng

William T Rericha

Puneet Sharma

Sheron Honarkhah

Ramakanth Alapati

Jingyi Bai

Zengtao “Tony” Liu

Tyler A Lowrey

Benham Moradi

Zengtao T Liu

Jim J Browning

Michael J Westphal

James J Alwan

Richard L Stocks

Glen F Hush

Jimmy J Browning

Ji Ung Lee

Hyuntae Kim

Sanh D Tang

Stephen L Casper

Eugene H Cloud

Fred D Fishburn

Zhongyi Xia

Troy V Gugel

Tian Zhang

J Ung Lee

David A Carthey, Jr

Raman Alapati

Jingyi (Jenny) Bai

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated circuit fabrication

An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.

Integrated circuit having pitch reduced patterns relative to photoithography features

Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch.

Methods for fabricating contacts of semiconductor device structures and methods for designing semiconductor device structures

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Pitch reduced patterns relative to photolithography features

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.

A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact that is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.

Semiconductor devices including fine pitch arrays with staggered contacts

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Meridian, ID, United States of America

John K Lee