International Business Machines Corporation

Globalfoundries Inc.

John K Koehler

Hayden C Cranford, Jr

Steven John Baumgartner

Todd Edwin Leonard

Carrie Ellen Cox

Steven Elliott Mikes

John Joseph Bergkvist, Jr

Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLKand CLK), where the pulse rate of CLKis slower than that of the CLKand greater than that of CLK. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLKbased on CLKand N-phases of the CLKand a second multi-phase pulse generator can generate N-phases of CLKbased on CLKand N-phases of CLK. Furthermore, additional registers can optionally use the N-phases of CLKto further generate N sets of M-phases of the CLK. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.

Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods

Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Aligning FIFO pointers in a data communications lane of a serial link

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Raleigh, NC, United States of America

John K Koehler