Broadcom Corporation

Broadcom Company

Immedia Semiconductor, Inc.

John K Iler

Stephen Elliott Gordon

Douglas Mark Chin

Daniel Backer Grunberg

Tim Hellman

Ronald Laidley

One example configuration as discussed herein includes a multi-stage image processing system. A first stage image processor in the multi-stage image processing system analyzes a first window of settings produced by an array of sensor elements in an image sensor. The first stage image processor scales one or more color ranges to detect defective sensor elements and produces corrective values on an as-needed basis. A second stage image-processing resource processes a second window of settings including original settings and/or substitute settings as produced by the first stage image processor. The second stage image processor applies a debayering algorithm to the second window of values to produce final display settings for the sensor elements.

Image processing

Streams of data are processed. A stream of data including a plurality of encoded symbols is received. Symbols from a first subset of the encoded symbols are processed contemporaneously to determine a second subset of encoded symbols, each of which uses a common coding context. At least one symbol from the second subset is evaluated to determine the common coding context. The common coding context is used to process the second subset of encoded symbols.

Processing data streams

A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.

System and method for fully digital clock divider with non-integer divisor support

Bursts of data are managed. Data is stored in a machine readable memory device a first time at a first memory address. The machine readable memory device has one or more burst boundaries. The first memory address has a first alignment with respect to the burst boundaries. The data is stored in the machine readable memory device a second time at a second memory address. The second memory address has a second alignment with respect to the burst boundaries.

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Burlington, MA, United States of America

John K Iler