Cyrix Corporation

Cisco Technology, Inc.

National Semiconductor Corporation

John K Eitrheim

Richard B Reis

Steven C McMahan

Christopher E White

Mark W Bluhm

Marc A Quattromani

Jeffrey S Byrne

Douglas Ewing Duschatko

Robert D Maher, Iii

Thomas B Brightman

Jeffrey A Huxel

Fred Dunlap

Lawrence H Hudepohl

Steve McMahan

Tai Dinh Ngo

Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Testing self-repairing memory of a device

A method for processing data is provided that includes receiving a first request in a first clock cycle from a processor for access to a first data segment corresponding to a first address included in the first request. A second request for access to a second data segment corresponding to a second address included in the second request is received during a second clock cycle. The second data segment is disabled from being communicated to the processor and the first data segment is communicated to the processor in response to the second request.

System and method for processing data in a memory array

A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.

High speed processor for operation at reduced operating voltage

Independent functional units are clocked by a clock source generator having at least two adjustable delay lines for independently adjusting the duty cycles of at least two clocks so that speed path margins are individually optimized for each functional unit.

Multiple clock source generation with independently adjustable duty

A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.

Programmable phase shift clock generator

An adjustable duty cycle clock generator has first and second delay lines coupled to receive an input clock and cascaded to first and second edge detectors, respectively. The second delay line has a programmable delay and the first and second edge detectors are further coupled to set and reset inputs on an S-R latch to generate an adjustable duty cycle clock with independently adjustable high and low times proportional to the induced delays of the first and second delay lines.

Adjustable duty cycle clock generator

A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first and a second port make data read, data write, and instruction fetch requests to/from the shared interleaved memory by way of asserting a priority signal, an address, and an operand size which are decoded to discern which, if any, memory banks in the interleaved shared memory are needed. In the event of a bank request conflict, the highest priority requester gets all its requested banks and the losing requester gets all nonconflicting requested banks. After the banks in the interleaved memory are allocated, a signal identifying that the losing requester did not receive all its requested banks is generated which does not impact the delay in the data path and accordingly, the losing requester resubmits its request on the next cycle.

Interleaved memory conflict resolution with accesses of variable bank

An adjustable duty cycle clock generator is disclosed having a single delay line cascaded to a multiplexer and first and second edge detectors which respectively drive set and reset inputs on a S-R latch to produce an adjustable duty cycle clock signal.

Single delay line adjustable duty cycle clock generator

An improved sense amplifier is disclosed employing bleeder and dampening devices coupled in a robust feedback configuration for maintaining a relatively narrow and stable voltage level above the high threshold of the sense amplifier.

Sense amplifier

A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.

Coprocessor interface supporting I/O or memory mapped communications

An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Clock multiplication circuit and method

An integrated circuit, such as a microprocessor or math co-processor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input clock signal is disclosed. The clock generator circuit includes a programmable delay stage having fixed and variable portions. The fixed portion preferably includes a series of logic elements of various types (NOR, NAND, NOT, pass gates, etc.), selected to match the worst case clock phase delay and which match speed variations as a function of voltage, temperature or processing conditions. The variable portion of the delay stage selects a propagation delay by way of programmable elements (e.g., mask programmable); multiplexers may be included therein to allow selection of the delay in a test mode. The high frequency clock is generated by a circuit having a set input receiving the input clock signal and a reset input receiving the output of the programmable delay stage; as a result, the output clock signal duty cycle depends upon the propagation delay through the programmable delay stage, and not upon the duty cycle of the input clock signal. A frequency divider may also be provided to generate a lower frequency clock based on the input clock signal. In addition, the set and reset circuits may be disabled in a non-clock doubling mode, in which another frequency divider may be enabled for generating an output clock signal.

Stable internal clock generation for an integrated circuit

A bus precharge circuit is provided that precharges a bus line or node as an inverse function of the precharge level already attained on the bus line, such that the precharge level on the bus line is gradually approached. The precharge circuit charges the bus line to a midpoint between high and low logic states. The preexisting state of the bus line is stored and is used to select one of two voltage supplies to which the bus line may be partially pulled up or down. The switchpoint of a precharge circuit sensing gate is set to be equivalent to the switchpoint of the receiving gate of receiver on the bus line.

Growing community of inventors

Plano, TX, United States of America

John K Eitrheim