International Business Machines Corporation

John Joseph Szarek

Yuan-Chang Lo

Dennis L Moeller

John K Langgood

Wan Lin Leung

Kimberly Kibbe Sendlein

Gerald George Isaac

Edward Yee

A computer system that has a main memory and a writeback cache memory also has an I/O device capable of data streaming. A memory controller responds to signals that the I/O device will perform a burst transfer of data to the main memory and blocks potential writebacks from the cache memory to the I/O device. Potential writing over of the data from the I/O device by a flushed cache line written back to the main memory is thereby prevented. The system performance is increased since the data from the I/O device can be written to the main memory without waiting for a snoop cycle and a writeback to be performed.

Computer system with a device for selectively blocking writebacks of

A microcomputer system has a first, low order address, memory soldered to the planar printed circuit board and can accept further memory pluggable into a socket on the board. At power on self test, the memories are tested, and, if an error is detected in the first memory, this memory is disabled by directing the lowest order memory addresses to the second memory and reducing the highest order addresses by the number of locations in the first memory.

Memory re-mapping in a microcomputer system

Growing community of inventors

Cary, NC, United States of America

John Joseph Szarek