International Business Machines Corporation

John Joseph Bergkvist, Jr

Todd Edwin Leonard

Carrie Ellen Cox

Hayden C Cranford, Jr

Michael Terrell Vanover

Steven Mark Clements

Serafino Bueti

Francis A Kampf

Donald E Carmon

Douglas Thomas Massey

John K Koehler

Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Aligning FIFO pointers in a data communications lane of a serial link

Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver.

Adaptable receiver detection

A source-series terminated ('SST') driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization

A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.

Simulation of digital circuits

A system for providing a time-based interrupt signal to a processor for executing a real time interrupt event with reduced interrupt latency, involves: a first programmable counter, which is capable of interrupting the processor by generating an interrupt signal on a regular time period based on the decrementing of an initial count value loaded therein, which value is re-loaded in the counter when the count is exhausted and the interrupt signal is generated; one or more second programmable counters, also having initial count values loaded therein that are decremented, and each of which, if the count is exhausted before that of the first counter, will not allow certain types of instructions or events, respectively associated with each second counter, to execute, if the execution of such instructions or events would cause an unwanted latency in the interrupt caused by the interrupt signal from the first counter.

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Williston, VT, United States of America

John Joseph Bergkvist, Jr