Teradyne, Inc.

John Joseph Arena

Anthony J Suto

Joseph Francis Wrinn

Eric Lenhart Truebenbach

John P Toscano

Jiann-Neng Chen

Richard P Davis

David John Lind

Teresa P Lopes

Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

Method and apparatus for bond wire testing in an integrated circuit

An example test fixture, which interfaces a tester and a unit under test (UUT), includes the following: first electrical contacts that face the tester; second electrical contacts that face the UUT; a substrate made of sections of printed first material, with the first material being electrically non-conductive, and with the substrate being between the first electrical contacts and the second electrical contacts; and structures through the substrate, with the structures including sections of second material, with the second material being electrically conductive, and with at least one of the structures electrically connecting a first electrical contact and a second electrical contact.

Test fixture

An example system for testing electronic assemblies (EAs) may include carriers for holding EAs and slots for testing at least some of the EAs in parallel. Each slot may be configured to receive a corresponding carrier containing an EA and to test the EA. An example carrier in the system may include a first part and a second part. At least one of the first part and the second part include a first structure, and the first structure is movable to enable electrical connection between an EA and an electrical connector.

Electronic assembly test system

Analog test instrument architecture for performing functional testing of electronic circuit assemblies is disclosed. The analog test instrument includes a plurality of identical channels, each channel including circuitry for driving test stimuli and measuring responses at one node of a circuit assembly under test. The driver and measurement circuitry in each channel implement functions that traditionally have been implemented in a test system using discrete instruments. The analog test instrument further includes a master clock reference, which is used for synchronizing the operation of the driver and measurement circuits. Each channel further includes triggering circuitry for distributing trigger events within the channel and to the other channels; and, an input buffer, which is shared by the measurement circuits in the channel. The synchronized operation, distributed trigger events, and shared input buffers are used to improve the correlation of measurements made during functional testing.

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Reading, MA, United States of America

John Joseph Arena