Qualcomm Incorporated

John Jong-Hoon Lee

Young Kyu Song

Xiaonan Zhang

Uei-Ming Jow

Sangjo Choi

Francesco Carrara

Chang-Ho Lee

Paragkumar Ajaybhai Thadesar

Xiaoju Yu

Daniel F Garcia

Mark A Kuhlman

Supatta Niramarnkarn

Peng Song

Fnu Suraj Prakash

Ashish Alawani

Kinfegebriel Amera Mengistie

Jeongkeun Kim

Nikhil Raman

A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor through the second inductor.

Package comprising substrate with coupling element for integrated devices

A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

Package comprising a solder resist layer configured as a seating plane for a device

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive 'fence' that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Flip-chip employing integrated cavity filter, and related components, systems, and methods

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San Diego, CA, United States of America

John Jong-Hoon Lee