Integrated Circuit Systems, Inc.

John J Wunner

Joseph T Gallagher, Jr

A dual dot clock signal generator consisting of two similar programmable phase locked loops simultaneously generates a video clock signal and a memory clock signal. Both the video clock signal and the memory clock signal may have one of several different frequencies. The generator includes circuitry which detects when one of the selected frequencies is identical to or a submultiple of the other. The comparison circuitry which detects this condition acts to change the frequency of one of the clock signals, and supplies the other clock signal in its place. Both the video clock signal generator and the memory clock signal generator are programmable via their respective internal memories, and the internal memory of the video clock signal generator carries additional information which identifies those video frequencies which are identical to or a submultiple of the frequencies available from the memory phase locked loop. By substituting the memory clock signal or a divided version of the memory clock signal for the conflicting video clock signal and changing the frequency of the VCO within the video phase locked loop, the problem of cross-interference between the two clock signals is eliminated.

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Warrington, PA, United States of America

John J Wunner