Intel Corporation

John J Vranich

Vinodh Gopal

Wajdi K Feghali

Nitin V Sarangdhar

William A Stevens, Jr

Gilbert M Wolrich

Kirk S Yap

Erdinc Ozturk

Daniel Cutter

Pierre Laurent

Robert P Ottavi

Andrew Milne

Vindoh Gopal

Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks&#x2014;e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks. Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.

Secure replay protected storage

A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability &#x3c;2) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.

Method and apparatus for testing mathematical algorithms

An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.

High performance raid-6 system architecture with pattern matching

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West Roxbury, MA, United States of America

John J Vranich