Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Gm Global Technolgoy Operations, Inc.

North Star Innovations Inc.

John J Vaglica

William C Moyer

Charbel Khawand

Mieu Van Vu

Jianping Tao

David Jeffery Hayes

Christopher K Y Chun

Arnaldo R Cruz

Mark E Elledge

Arthur M Goldberg

Stanley E Groves

Vernon B Goler

Brian F Wilkie

Tuongvu Van Nguyen

Ryan D Bedwell

Jose G Corleto-Mena

Joseph Charles Circello

James B Eifert

Peter Jeremy Wilson

Daniel M McCarthy

Avraham Horn

Ori Goren

Roy M Shor

Qadeer A Qureshi

John D Mitchell

Jeffrey William Scott

Joseph Staudinger

Ilan Pardo

Christopher K Chun

Thomas E Tkacik

Hiroyuki Sugiyama

Lawrence Loren Case

Arvind Kaushik

Paul Richard Hart

Ramanujam Srinidhi Embar

John H Arends

Bradley Gene Burgess

Mark W McDermott

Grady L Giles

Michael D Fitzsimmons

Asaf Ashkenazi

Oded Norman

Wallace B Harwood, Iii

Bernard J Pappert

David H Hartley

Somvir Dahiya

Brian M Millar

Carlin R Covey

Yoram Salant

Jay A Hartvigsen

John P Dunn

Paul McAlinden

Thomas K Johnston

Rodney D Ziolkowski

Rand L Gray

Arvind S Arora

James S Thomas

Nicholas Justin Mountford Spence

William P Laviolette

Mark D Redman

Arindam Sinha

Moshe Refaeli

James C Smallwood

Adi Sapir

John Mark Boyer

Danny Shterman

William Clayton Bruce, Jr

Thomas Edward Oberhauser

Mieu Van V Vu

Yuhang Zhu

C David Wright

Ruchir Chhabra

Troy E Mackie

Alistair N Muir

Arnold R Cruz

Sreedharan Bhaskaran

Allen Guoyuan Deng

Puneet Wadhawan

A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface combines the digital data sample and the control bit(s) into one or more data packets and sends the data packet(s) over a signal line. A serialized receive interface receives the transmitted data packet(s) from the signal line and produces a reconstructed digital data sample and the control bit(s) from the transmitted data packet(s). A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

Methods and systems for communicating data and control information over a serial link

A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

Apparatus, system and method for controlling packet data flow

A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Programmable direct memory access channels

A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link () by providing a hardware control mechanism (-) at a local radio base station subsystem () connected in a CPRI daisy chain configuration between a downstream RE device () and an upstream REC device () for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.

Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

A method and apparatus for a radio base station () aligns IQ data blocks for transmission over multiple radio frequency (RF) signal paths () between a base station controller () and a plurality of antennas () at the base station by determining a path delay () for each RF signal path, and then transmitting IQ data blocks from JESD 204 transmit interfaces (-) over each RF signal path ahead of a first predetermined time slot by an advance time period equaling the path delay for each RF signal path, thereby aligning IQ data block signaling to the first predetermined time slot at the antennas.

Method and system for phase compensation in multi-path communication device

A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layerprocessor operations, layerprocessor operations, and layerprocessor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Cellular modem processing

A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.

Switch-mode amplifier

A method and apparatus automatically maintains a JESD204 serial data link () as active by using an idle signal () and multiplexer selection circuit () to selectively switch signal data samples () and dummy samples () onto a serial interface input to a JESD module () for serialization into a plurality of symbols for transmission over the JESD204 serial data link () in response to a transmit clock signal () so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.

Method and system for low power transmission and data alignment

Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party.

Authenticated debug access for field returns

A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

New approaches for providing communication between multiple masters () and one or more shared resources () are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry () may be used to provide steering for additional signals such as interrupts. Other shared resources () may use more centralized circuitry () to perform a steering function for additional signals.

Communication steering for use in a multi-master shared resource system

The invention concerns a method () for employing adaptive event codes. The method includes the steps of generating () at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing () the adaptive event code in at least one table (), running () the table in which the adaptive event codes are at least initially disabled and enabling () the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (). The method can further include the step of ignoring () the adaptive event codes during the running step when the adaptive event codes are disabled.

Method and system for employing adaptive event codes

A CPU has a powerdown mode in which most of the circuitry does not receive power. Power-up, coming out of powerdown, is achieved in response to receiving an exception. Because most of the state information that is present in the CPU is not needed in response to an exception, there is no problem in removing power to most of the CPU during powerdown. The programmer's model register file and a few other circuits in the CPU are maintained in powerdown, but the vast majority of the circuits that make up the CPU: the execution unit, the instruction decode and control logic, instruction pipeline and bus interface, do not need to receive power. Removing power from these non-critical circuits results in significant power savings during powerdown. The powered circuits are provided with a reduced power supply voltage to provide additional power savings.

CPU powerdown method and apparatus therefor

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Austin, TX, United States of America

John J Vaglica