Eastman-kodak Company

John J Uebelacker

Kenneth Alan Parulski

Jeffrey Alan Small

Seiichi Mizukoshi

Masaki Izumi

Clay A Dunsmore

Kenneth D Kieffer

David M Charneski

John K Lynch

Richard A Wanzenried

A flash quench controller for a camera having a flash unit includes a light detector for producing a signal, an integrator for integrating the signal from the detector and producing an integrated signal, a comparator for comparing the integrated signal to a reference value, and means for quenching the flash unit when the integrated signal reaches the reference value. By using a pulse signal having a variable pulse width to programmably set the reference value, many different quench time values can be easily established. The flash unit may also be quenched by setting a maximum flash time value. The flash is automatically quenched if this flash time value is reached before the integrated signal level reaches the programmed reference value.

Digitally controlled quench flash circuit

A bus interface device for an application specific integrated circuit handles more than two different clock frequencies and allow for real time switching between the clock frequencies by subsystems of the application specific integrated circuit. In a preferred embodiment, a master state machine is provided that includes a plurality of control input lines and a plurality of control output lines, and a plurality of synchronizing state machines each coupled to one of the control output lines of the master state machine and to a separate clock frequency line. The master state machine, based on signals applied to the control input lines, selectively enables the synchronizing state machines to supply the different clock frequencies to the subsystems of the application specific integrated circuit.

Asic bus interface having a master state machine and a plurality of

The present invention is a sample rate converter in which a weighted filtering operation is performed. This operation stores a pixel stream in a random access memory (RAM) 30. During conversion pointers stored in counter 38 and register 40 are used to select the pixels from the RAM which are then multiplied by filter weights and accumulated. A counter 44 and mapping unit 46 select the weight being multiplied. The multiplication is performed by a lookup table read only memory (ROM) 32 that stores the results of the pixel-weight multiplication for all combinations of pixels and weights for each sample rate. An accumulator 33 stores the results of the multiplication until all multiplications have occurred at which point the filtered pixel is output. The output of the lookup table 32 is controlled by the pixel value, the coefficient selected and the table or map selected. The lookup table stores symmetric weights for as many conversion rates as desired. The mapping unit 46 maps a sequential coefficient count to a coefficient identifier which is non-sequential and symmetric allowing the size of ROM 32 to minimized and the number of address lines provided to the ROM 32 to be minimized.

Sample rate converter circuit for image data

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Rochester, NY, United States of America

John J Uebelacker