Motorola Corporation

International Business Machines Corporation

John J Stankus

Karl G Hoebener

Jeffrey T Wetzel

Joy Kimi Watanabe

Boyd M Fry

Burt Wayne Fowler

Semiconductor devices that include mismatched lattice crystal interfaces are produced by edge growth heteroepitaxy from a crystal with a small surface area to decrease crystal mismatch strain, achieving a crystal with reduced displacement faults. Mismatched crystal lattices are also deposited on a deformable thin membrane of semiconductor material to reduce strain in growing crystal and to reduce displacement faults to achieve a monolithic crystal structure.

Edge growth heteroepitaxy processes with reduced lattice mismatch strain between a deposited semiconductor material and a semiconductor substrate

An apparatus which aligns a fiber core to a detector on an integrated circuit has a transmission material connecting them which steers the light provided through the fiber core to the detector even in the case of misalignment. The transmission material chosen has a characteristic of being able to have the spatial distribution of its index of refraction altered by electrical means. In this case, an electric field is applied in the area surrounding the path from the fiber core to the detector. Thus, even if the fiber core is not aligned to the detector, the light will be directed from the fiber core to the detector due to the path being surrounded by a lower index of refraction than the path itself. Thus, there is very little loss due to misalignment between the fiber core and the detector.

Method and apparatus for aligning a waveguide to a device

A method for forming a buried optical mirror in an integrated circuit (IC) begins by forming an opening (18) within a substrate (12). The opening (18) is then filled with a plurality of dielectric layers (20-26) that have different indexes of refraction whereby a Bragg reflector can be formed. A chemical mechanical polishing (CMP) process is then used to planarize the layers (20-26) such that these layers (20-26) only reside within the opening (18) whereby a mirror is formed. Lateral selective epitaxial growth, polysilicon deposition and recrystallization, or wafer bonding is then used to form a single crystalline or near single crystalline semiconductive material (32b) over a top of the substrate (12) and the reflecting mirror. Photodevice(s) are then formed over the mirror in the region (28) of material (32b) whereby reflecting mirror (20-26) will improve the quantum efficiency and speed of the photodevice(s).

Method of formation of buried mirror semiconductive device

A buffer film (154, 164) is formed over an underlying film (153, 162) to protect that underlying film (153, 162) from damage during a removal sequence, such as polishing. Scratches, gouging, smearing that can occur to the underlying layer (153, 162) are less likely to occur because of the presence of the buffer film (154, 164). In some embodiments, an insulating film (162) is to be protected. The buffer film (164) is formed over the insulating film (162), and the insulating and buffer films (162 and 164) are patterned. During a subsequent conductive layer polishing operation in an embodiment, most of the buffer film (164) is removed. In still another embodiment, a buffer film (154) is formed over a conductive layer (153) to protect it during 'gap fill' process sequence. Although residual portions of the buffer film (154, 164) are usually removed, in some instances, those residual portions can remain if there are no significant adverse affects.

Process for forming a semiconductor device

A method for forming semiconductor device (1) that includes providing a substrate (10) having a metal interconnect (12), depositing a via interlevel dielectric (ILD) layer (20) over the substrate (10) and the metal interconnect (12), etching the via ILD layer (20) to form a via (30) over the metal interconnect (12), depositing a trench ILD layer (32) over the via ILD layer (12) and the via (30), etching the trench ILD layer (32) to form a trench (40), the trench (40) being contiguous with the via (12), and depositing a metal (44) so as to fill the via (30) and the trench (40), and provide electrical connection with the metal interconnect (12).

Method of forming a semiconductor device having dual inlaid structure

A technique for one step solder application through a mask to a printed circuit board (PCB) having pads for surface mountable components and through holes for a leaded components is disclosed wherein the amount of solder deposited on the pads and in the holes is simultaneously, independently controlled as a function of mask thickness, blade hardness and blade to mask angle.

Solder deposition control

A packaging technique for finely leaded electronic devices for attachment by surface methods to printed circuit boards is disclosed wherein the leads are imbedded in solder foil prior to the completion of lead forming operations so as to maintain planarity of the leads and to prevent damage thereto during handling, placement and attachment processes.

Growing community of inventors

Austin, TX, United States of America

John J Stankus