Other

Lsi Logic Corporation

Symbios, Inc.

John J Seliskar

Todd A Randazzo

David W Daniel

John W Gregory

James P Yakura

Dim Lee Kwong

Derryl D J Allman

Derryl D Allman

Verne C Hornback

A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.

Castellated gate MOSFET tetrode capable of fully-depleted operation

A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascade structure. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming regions. Both the primary and secondary channel-forming regions include pluralities of thin, spaced, vertically-orientated semiconductor channel elements that span longitudinally along the device between the source and drain regions. First and second gate structures are provided in the form of pluralities of spaced, castellated first and second gate elements interposed between the primary and secondary channel elements, respectively, with first and second top gate members interconnecting the first and second gate elements at their upper vertical ends to cover the primary and secondary channel elements. The adjoined primary and secondary channel elements are super-self-aligned from the first and second gate elements to the source and drain regions. Finally, first and second dielectric layers separate the primary and secondary channel elements from their respective gate structures.

A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body. The channel-forming region within the isolated castellated-gate MOSFET region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. One or more of the trench isolated regions may contain at least one type or polarity of logic and/or memory computing device. Alternately or additionally, one or more type of Logic and/or memory device may be incorporated within vertically displaced regions above the active body region of the semiconductor wafer, embedded within Interlevel Dielectric Layers.

Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof

A castellated-gate MOSFET I/O device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, and a channel-forming region is also disposed therein between the source and drain regions. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming region. The channel-forming region includes a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements, and a top gate member interconnects the gate elements at their upper vertical ends to cover the channel elements. The conductive channel elements are super-self-aligned from the gate structure to the source and drain regions. Finally, a dielectric layer separates the conductive channel elements from the gate structure.

Castellated gate MOSFET device capable of fully-depleted operation

A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. Trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements. The gate structure also includes a top gate member which interconnects the gate elements at their upper vertical ends to cover the channel elements. Finally, a dielectric layer is provided to separate the conductive channel elements from the gate structure.

Fully-depleted castellated gate MOSFET device and method of manufacture thereof

A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements. The gate structure also includes a top gate member which interconnects the gate elements at their upper vertical ends to cover the channel elements. Finally, a dielectric layer is provided to separate the conductive channel elements from the gate structure.

A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface. A second well region is disposed in the semiconductor substrate below the channel region, the second well region being of the first conductivity type having a second average dopant concentration. A buried electrode region is disposed below the source and drain regions between the second well region and the channel region. The buried electrode region has a dopant of the first conductivity type at a concentration which is greater than both the first and second dopant concentrations of the channel region and the second well region, respectively. Finally, a gate is disposed over the channel region with the buried electrode creating a low gate threshold voltage with significantly reduced likelihood of punch through.

Low threshold voltage MOS transistor and method of manufacture

A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically. The relatively narrow channel widths allow fully-depleted and fully-inverted conductivity characteristics which enhance the conductivity characteristics of the FET despite its reduced size, without silicon on insulator (SOI) constructions or epitaxial substrates.

Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET

High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

MeV implantation to form vertically modulated N&plus; buried layer in an NPN bipolar transistor

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

Integrated circuit device having a capacitor with the dielectric

Use of MEV implantation to form vertically modulated N+ buried layer in

A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event to diffuse an emitter region of the bipolar transistor. The emitter is diffused or implanted to a depth greater than the depth to which a source and a drain region of the MOSFET are diffused. By using only the base region and source/drain region masks, and developing in sequence, each of two coatings of photoresist applied on top of one another, an access opening to the emitter region is define solely by the co-location of openings in each of the two coatings, thereby allowing the emitter region to be separately and additionally implanted. The access to the base region for the additional implication is achieved using only a few additional photo-ops and not as a result of using an additional emitter mask.

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Fort Collins, CO, United States of America

John J Seliskar