International Business Machines Corporation

Other

John J Reilly

Bartholomew Blaner

Bulent Abali

Jeffrey A Stuecheli

Ganesh Balakrishnan

Paul David Kartschoke

Kenneth Anthony Lauricella

Manikandan Viswanath

Dorothy Marie Thelen

Steven E Charlebois

Craig B Agricola

Sebastian Theodore Ventrone

Gordon Taylor Davis

Hubertus Franke

Baiju Dhirajlal Mandalia

William R Robinson, Jr

Michael G Holung

Aspects of the disclosure provide for mechanisms data anonymization. A method of the disclosure includes: receiving, by a processing device, a user input initiating anonymization of a first electronic document, wherein the first electronic document comprises at least one first data item relating to personally identifiable information and at least one second data item not related to the personally identifiable information; in response to receiving the user input, generating a second electronic document, wherein the second electronic document comprises a digital fingerprint of the first electronic document and the at least one second data item; and transmitting, to a server, the second electronic document as an anonymized version of the first electronic document.

Methods, systems, and media for data anonymization

Aspects include copying a plurality of input data into a buffer of a processor configured to perform speculatively executing pipelined streaming of the input data. A bit counter maintains a difference in a number of input bits from the input data entering a pipeline of the processor and a number of the input bits consumed in the pipeline. The pipeline is flushed based on detecting an error. A portion of the input data is recirculated from the buffer into the pipeline based on a value of the bit counter.

Speculative data processing and recovery

An array processor includes a managing element having a load streaming unit coupled to multiple processing elements. The load streaming unit provides input data portions to each of a first subset of the processing elements and also receives output data from each of a second subset of the processing elements based on a comparatively sorted combination of the input data portions provided to the first subset of processing elements. Furthermore, each of processing elements is configurable by the managing element to compare input data portions received from either the load streaming unit or two or more of the other processing elements, wherein the input data portions are stored for processing in respective queues. Each processing unit is further configurable to select an input data portion to be output data based on the comparison, and in response to selecting the input data portion, remove a queue entry corresponding to the selected input data portion. Each processing element may be further configured to provide the selected output data portion to either the managing element or as an input to one of the processing elements.

Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements

Responsive to a data lookup in a buffer triggered for a search string, a processor searches for a selection of pairs from among multiple pairs of a hash table read from at least one address hash of the search string and matching at least one data hash of the search string, each row of the hash table assigned to a separate address hash, each of the pairs comprising a pointer to a location in the buffer and a tag with a previous data hash of a previously buffered string in the buffer. The processor identifies, from among the selection of pairs, at least one separate location in the buffer most frequently pointed to by two or more pointers within the selection of pairs. The processor, responsive to at least one read string from the buffer at the at least one separate location matching at least a substring of the search string, outputs the at least one separate location as the response to the data lookup.

Efficient and accurate lookups of data by a stream processor using a hash table

Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspension. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Suspend and resume in a time shared coprocessor

A method for sorting data in an array processor. Each of a first tier of processing elements in the array processor receives data inputs from a load streaming unit. Each of the first tier processing elements compares input data portions received from the load streaming unit, wherein the input data portions are stored for processing in respective queues. The first tier processing elements select one of the input data portions to be an output data portion based on the comparison, and in response to the selection, remove a corresponding queue entry and request next input data from the load streaming unit. Each of the first tier processing elements further provides the output data portion as an input data portion to a second tier processing element that generates output data based on a comparison of output data received from at least two first tier processing elements.

Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

An array processor includes a managing element having a load streaming unit coupled to multiple processing elements. The load streaming unit provides input data portions to each of a first subset of processing elements and receives output data from each of a second subset of the processing elements based on a comparatively sorted combination of the input data portions. Each processing element is configurable by the managing element to compare input data portions received from the load streaming unit or two or more of the other processing elements. Each processing unit can further select an input data portion to be output data based on the comparison, and in response to selecting the input data portion, remove a queue entry corresponding to the selected input data portion. Each processing element can provide the selected output data portion to the managing element or as an input to one of the processing elements.

Operation of a multi-slice computer processor that includes a plurality of execution slices. Operation of such a computer processor includes: matching one or more sub strings of a data string to one or more substrings of a data set; determining that a particular substring of the one or more substrings of the data string corresponds to a highest priority value among one or more priority values mapped to one or more encodings for the one or more substrings of the data string; and encoding, in dependence upon the particular substring of the data string corresponding to the highest priority value, the data string into an encoding that encodes the particular substring of the one or more substrings of the data string.

Operation of a multi-slice processor implementing priority encoding of data pattern matches

Techniques for creating a dynamic Huffman table in hardware are provided. In one aspect, a method for encoding data includes the steps of: implementing dynamic Huffman tables in hardware representing a plurality of Huffman tree shapes precomputed from a sample data set, wherein the Huffman tree shapes are represented in the dynamic Huffman tables by code length values; upon receipt of input data, writing symbols and their counts from the input data to the dynamic Huffman tables; calculating a score for each of the dynamic Huffman tables with the symbols and counts from the input data, wherein the score is based on the code length values of the precomputed Huffman tree shapes and the counts from the input data and selecting a given one of the dynamic Huffman tables having a lowest score for encoding the input data. A process for implementing the present techniques in SRAM is also provided.

Creating a dynamic Huffman table

Systems and methods are provided for data comparisons in a compression algorithm to optimize the compression of data. An exemplary method includes receiving input data. The method further includes generating a hash table address for the input data. The method further includes obtaining a pointer associated with the hash table address. The method further includes reading a data library with the pointer to obtain an associated piece of historical data. The method further includes comparing the historical data to the input data to determine a match.

Compression pattern matching

A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).

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John J Reilly