Archive Corporation

John J Quintus

Michael S Sheehan

William A Buchan

Tuong M Vu

An apparatus and a method for calibrating the write current applied to a write head (110, 114) in a tape drive (100) finds the peak value of the write current applied to the tape head (110, 114) (i.e., the write current value providing the maximum read voltage amplitude on a tape (104)) by indirectly measuring the voltage sensed by a read head (112, 115). The apparatus includes a digital write current control circuit (170, 160) that applies a write current having a magnitude responsive to a digital write current value. An amplifier (190) in a read circuit (180, 182, 184, 190, 196) has a gain responsive to a digital read gain value. The method includes the steps of sampling the output of a pattern detector (146) (e.g., a gap detector) as the digital read gain value is adjusted for each of a number of digital write current data values applied to the write current control circuit (170, 160). The digital read gain value is adjusted to provide a predetermined range of the number of samples wherein the pattern corresponds to a predetermined pattern. The digital read gain value for each digital write current value is inversely related to the amplitude of the signal recorded on the tape (104). The sampled digital read voltage gain values are then stored. The digital write current value corresponding to the minimum stored digital read gain value also corresponds to the peak value of the actual write current. The digital write current value corresponding to the minimum digital read voltage gain value is then selected and stored as the calibrated digital write current.

Apparatus and method for automatic write current calibration in a

A phase locked loop circuit including ramp generating circuitry for generating a dual slope ramp signal having alternating positive and negative slopes that are controlled by the level of the control signal, and sampling circuitry responsive to sample command pulses for providing a sample output representative of the level of the dual ramp signal at the time of sampling. The sample output is provided to a loop which provides the control signal for the ramp generating circuit. Also disclosed is a phase locked loop having ramp generating circuitry for generating a ramp signal, and track and hold circuitry having a plurality of track/hold capacitors that are controlled to track the ramp voltage or hold the ramp signal voltage in response to a sample command signal, such that only a capacitor that is tracking is switched to hold the ramp voltage in response to the sample command signal.

Track and hold phase locked loop circuit

An apparatus for nullifying the differential output offset voltage between the outputs of a differential amplifier and for setting the DC levels of the outputs to a known reference voltage includes a circuit which cross-couples the opposing AC output signals to obtain only the DC components of each signal. The apparatus further includes a first operational amplifier to generate a compensation voltage from the DC components of the outputs of the differential amplifier proportional to the amount of offset between the DC components of the outputs of the differential amplifier. The compensation voltage is fed back to the offset control inputs of the differential amplifier to reduce the differential offset voltage to substantially zero volts. The apparatus further includes a dual voltage divider network having a second operational amplifier that supplies a variable reference voltage to one terminal of each leg of the voltage divider network. The outputs of the differential amplifier each provided to a respective other terminal of the dual voltage divider network. The second operational amplifier has a reference voltage on one of its inputs. A signal responsive to the common mode output voltage from the differential amplifier is provided to the other input. The second operational amplifier provides an output voltage that is responsive to the common mode voltage output from the differential amplifier. The output voltage from the second operational amplifier provided to the terminals of the dual voltage divider network varies such that the voltage outputs from the voltage divider network have a common mode voltage substantially equal to the reference voltage.

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Buena Park, CA, United States of America

John J Quintus