Vtc Inc.

Texas Instruments Corporation

Lucent Technologies Inc.

Other

Vtc Bipolar Corporation

John J Price, Jr

Tuan V Ngo

Craig Matthew Brannon

Donald Joseph Schulte

Jeremy R Kuehlwein

An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current directing circuit receiving the write signals and directing a write current to establish a write voltage between first and second write loci in a first or second excursion toward a first or second polarity in response to the first or second write signal. The first and second write loci are coupled with supply locus via an adjacent first or second impedance unit and a first or second switching unit. The first and second switching units are controlled at first and second control loci by the first and second write signals. First and second boost systems are coupled with the first and second control loci for boosting the write voltage toward the first and second polarities during first and second excursions.

Apparatus and method for applying write signals for driving a write head

A simplified comparator circuit () having hysteresis and lower power requirements for its implementation. The circuit () includes 2 minimum-sized MOSFETs (MN, MN) providing feedback from the circuit output to an input device (MN) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.

Method to implement hysteresis in a MOSFET differential pair input stage

A HDD write driver circuit () having a boost current overshoot programmed by a plurality of pull-up devices (MP, MP, MP, MP). The pull-up strength of an inverter () is adjustably selected by programming pull-up PMOS devices, and less power is dropped across a resistor (R) such that there is less boost current overshoot when an overshoot MSB is low.

Programmable overshoot for a servo writer

Disclosed is a circuit and method for generating a tail current for a main reader amplifier () input stage using a scaled master differential stage () with a given offset to force a given output current, preceded by a balanced stage () to get a balanced offset. Current must be set by a feedback arrangement in the dummy master stage () which is a scaled version of the main reader amplifier input stage (). The current derived in the dummy master stage (), when appropriately scaled and used as the tail current of the main reader amplifier () input stage provides a precisely controlled gain.

Tail current generator circuit for bipolar/MOS differential pair to set precise transconductance

A technique for presenting an optimally timed control signal to an upper H-switch driver in a fashion capable of achieving a very fast transition of the current in the inductive recording head. The technique also provides a current boost during the transition while resulting in minimized power consumption at other times.

System and method for enhancing write driver performance

A negative supply, low-voltage supply fault detection circuit is implemented without the need for a current mirror thereby providing for the elimination of inaccuracies generally associated with a current mirror, and resulting in less power consumption when compared with known negative supply, low-voltage detection circuits that employ a current mirror and associated support circuitry.

System and method for detecting a negative supply fault

Undershoot and overshoot control circuitry is provided in a write driver circuit to enhance its efficiency and ability to quickly change directions of write current through a write head. The undershoot and overshoot control circuitry includes: (1) an undershoot reduction circuit, which adds current to the write current when one head terminal has a voltage higher than the opposite head terminal and the input signals are in a certain state, indicating that the write current waveform is about to experience some level of undershoot; (2) an overshoot enhancement circuit, which adds current to the write current when one of the head terminals has a voltage lower than a predetermined threshold, indicating that the write current waveform is about to experience some level of overshoot; and (3) an overshoot reduction circuit, which provides a resistance between the head terminals in parallel with the write head to damp overshoot, when one of the head terminals has a voltage lower than a predetermined threshold, indicating that the write current waveform is about to experience some level of overshoot. The predetermined thresholds, the currents added to the write current, and the resistance provided are all programmable in one embodiment, so that the undershoot and overshoot of the write driver circuit may be precisely controlled for efficient operation.

Write driver circuit having programmable overshoot and undershoot

Turn-on and turn-off control circuitry are provided for a write driver circuit having first and second switching devices for directing current in opposite directions through a write head between first and second terminals in response to first and second input signals. The turn-off control circuitry includes first and second active devices coupled to the control elements of the respective first and second switching devices. The first and second active devices are operated to pull current from the control elements of the first and second switching devices in first and second current paths upon activation of appropriate input signals. First and second resistors are connected in the respective first and second current paths. The turn-on control circuitry includes a first resistor coupled between a control element of the first switching device and a fixed voltage and a second resistor coupled between a control clement of the second switching device and the fixed voltage. Active devices are coupled between the control elements of the first and second switching devices and the fixed voltage, the active devices each having a control element coupled to the control clement of the opposite switching device.

Write driver circuit having enhanced switching control circuitry

A magnetic recording control circuit for controlling current through a magnetic recording head includes a switch network, a signal coupler, and first and second voltage clamps. The switch network is connected to first and second magnetic recording head node regions and includes first, second, third, and fourth switches each having a variable magnitude conduction path and a control region. The signal coupler includes an input region and a plurality of output regions each connected to the control region of a corresponding switch. The first and second voltage clamps limit voltage differences between the magnetic recording head node regions and the control regions of the first and second switches.

Magnetic recording control circuit with voltage clamps

A simulation circuit has a simulation circuit path that simulates operation of the write current circuit path of a write current driver. A simulation transistor simulates operation of the driver transistor and a monitor circuit monitors current at the base of the simulation transistor to derive a compensation current based on variations in base current, including breakdown of the simulation transistor. The compensation current is combined with the driver current to derive the write driver current for the driver transistor of the write current driver. In another form, the simulation circuit path is a scaled-down electrical equivalency of the write current circuit path so that the simulation current is a scaled fraction of the write current and power requirements are reduced. In one form, current is added to the compensation current to accommodate unidirectional nature of current mirrors in the monitor circuit.

Breakdown voltage compensation circuit for write driver transistors

The present invention is a dual-input-to-single-output amplifier circuit having a processing amplifier, first and second coupling regions, first and second input impedance circuits, first and second feedback impedance circuits, first and second shunting impedance circuits. The processing amplifier has first and second input regions and an output region. The first and the second input regions each exhibit a relatively high circuit impedance. The output region exhibits a relatively low circuit impedance. The processing amplifier is capable of providing at the output region a signal in a first magnitude direction substantially similar to a signal provided at the second input region in the first magnitude direction but of a greater magnitude in the first magnitude direction. The processing amplifier is further capable of providing at the output region a signal in a second magnitude direction substantially similar to a signal provided at the first input region in the first magnitude direction but of a greater magnitude in the second magnitude direction. The first input impedance circuit is coupled between the first coupling regions and the first input region. The second input impedance is coupled between the second coupling region and the second input region. The first feedback impedance circuit is coupled between the output region and the first input region. The second feedback impedance circuit is coupled between the output region and the second coupling region. The first shunting impedance circuit is coupled between the first coupling region and a reference voltage terminal region. The second shunting impedance circuit is coupled between the second input region and the reference voltage terminal region.

Method to equalize input currents to differential-to-single-ended

A write driver, having a pair of head pins for connection to a write head, includes two push-pull buffer circuits connected respectively between first and second pull-up resistors and the control nodes of first and second upper drive transistors. The buffer circuits selectively charge and discharge the inherent capacitances of the upper drive transistors, thereby accelerating their turn on and turn off without diminishing head swing. Moreover, connecting the buffer circuits between the pull-up resistors and the upper transistors effectively isolates, or buffers, the pull-up resistors from the self-inductance voltages of the write head, reducing glitching in the write-head output signal.

Write driver with buffer circuits between pull-up resistors and upper

A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Multiplexer with CMOS break-before-make circuit

A programmable phase comparator comprises a switch circuit operable in response to first and second signals to provide an output signal representative of the phase relationship of the first and second signals. A reference signal is applied to the switch circuit to offset the output signal. A phase adjustment adjusts the phase relationship of the first and second signals so that the offset output signal is representative of a null condition. The switch circuit preferably is a Gilbert multiplier having a current source, an impedance means, and a transistor circuit connected between the current source and the impedance means. The transistor circuit has first and second inputs for receiving the first and second signals. The reference signal is input between the transistor circuit and the impedance means and is connected to an output. The output provides the output signal having a value based on the reference signal and the phase relationship of the first and second signals.

Programmable phase comparator

A system for writing servo information to a plurality of magnetic discs in a servo write mode, and for writing data to the plurality of magnetic discs in a data write mode in disclosed. The system includes a servo binary input buffer for receiving a mode signal and for directing the write signal based upon the mode signal. A first plurality of switches, coupled to the servo binary input buffer and to a disc select buffer, directs the write signal to a selected portion of a plurality of write heads. A second plurality of switches, coupled to the first plurality of switches, to the plurality of write heads, and to a head select buffer, supplies the write signal to one write head in the selected portion of the plurality of write heads during the data write mode, and supplies the write signal to one half of the write heads in the selected portion of the plurality of write heads during the servo write mode.

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Edina, MN, United States of America

John J Price, Jr