Motorola Corporation

John J Price

Ira G Miller

Robert C Rumbaugh

A translation circuit provides an output referenced to ground in response to either an ECL input or a TTL input. ECL or TTL supply voltages are selectively applied to first, second, third and fourth supply voltage terminals in accordance with the type of input signal received.

Circuit having an output referenced to a specific voltage in response to

A bit switch is provided for use in a digital-to-analog converter for providing a bit current to a summing bus. A first differential pair of switching devices are responsive to a digital input signal and provide first and second output signals to a second differential pair of switching devices that provide the bit current. First and second drive circuits are coupled between the first and second differential pair of switching devices for respectively slowing down the voltage transition of the first and second output signals for reducing glitches in the bit current.

Fast settling digital to analog converter bit switch

A voltage reference circuit for providing a temperature compensated voltage at an output thereof comprise a pair of transistor operated at different current densities for producing a first and second voltages having complementary temperature coefficients and circuitry for combining the two voltages to produce the temperature compensated voltage. A pair of load resistors are connected to the collectors of the two transistors for sourcing currents thereto and a feedback circuit, including a differential amplifier coupled to the respective collectors, provides a feedback signal for adjusting the potential on the bases thereof to maintain different current densities in the two transistors. A bias circuit operates in conjunction with the differential amplifier to bias the same in a balanced operating state whenever the currents in the transistors are substantially equal.

NPN band gap voltage reference

The input voltage signals to a comparison circuit may vary between levels substantial equal to the first and second supply voltages (e.g. typically 5 volts and ground). A first transistor circuit is coupled to a current mirror circuit and to an output node for supplying a mirrorable current to the current mirror circuit which in turn reduces the voltage at the output node when the first input voltage approaches the upper supply voltage, and supplies a current to the output to increase the voltage thereat when the second input approaches the upper supply voltage. A second transistor circuit is also coupled to the current mirror and to the output for supplying a mirrorable current to the current mirror means so as to reduce the voltage at the output when the second input voltage approaches ground, and supplies current to the output to increase the voltage thereat when the first input voltage approaches ground. The output node has coupled thereto a level shifting transistor and first and second follower transistors.

Comparator circuit having full supply common mode input

A circuit for use with interface systems for providing a threshold setting function wherein the system can be made to interface with T.sup.2 L or CMOS logic with either 5 or 15 volt power supply capabilities. The circuit comprises a pair of matched resistors coupled in series to one another. The first one of the resistors is returned to a select terminal via a first pair of diodes. The second resistor is returned to a terminal at which may be supplied a ground reference potential via a second pair of diodes. A source of current is provided that is coupled to the interconnection of the second resistor with the second pair of diodes. A threshold output is provided to the interface system at the interconnection between the serially connected resistors.

Logic select circuit

A bit switch for use in a digital-to-analog converter comprises three differential pairs of transistors. The first pair receives a digital input signal and a reference voltage signal. The second pair switches the bit current to either an output bus or to ground depending upon the state of the input signal. A third differential pair of transistors is coupled between the first and second pairs for minimizing adverse effects of fast input transitions and parasitic capacitance.

A current drive source circuit for providing current drive to a plurality of loads coupled thereto for reducing effects of power supply variations on the loads. The current drive source includes a reference circuit for producing a reference bias potential for biasing a load transistor. An internal current source comprising a split dual-collector PNP transistor provides collector current to the load transistor and also a feedback signal path to the emitter of the load transistor, which emitter electrode is coupled via a resistor to a ground terminal. The output of the current drive source is provided at the base electrode of the split dual-collector transistor.

Circuit providing improved rejection to power supply variations to

A monolithic amplifier circuit including a differential stage, a differential-to-single ended converter stage, a bias circuit and complementary push-pull output transistors is disclosed. The bias circuit is comprised of a current supply, two semiconductor bias devices and two current sinks. The junctions of the bias devices are connected in series across the junctions of the complementary output transistors to provide bias and to compensate for temperature and process variations in the output transistors. One of the bias devices and one of the current sinks are connected in one parallel path and the other bias device and the other current sink are connected in another parallel path through which most of the current from the current supply flows. This parallel connection enables utilization of minimum geometry bias devices in addition to facilitating precise and predictable control of the bias voltages and currents.

Bias circuit for complementary transistors

Combining a differential PNP transistor pair for receiving external digital signals with an NPN output transistor in an I.sup.2 L configuration connected to the output of the differential pair provides a simple, high-speed, and versatile digital logic to I.sup.2 L interface circuit. The interface circuit is applicable to almost any digital logic series and also to analog inputs as they provide inputs into I.sup.2 L circuitry.

I.sup.2 L interface with external inputs and method thereof

There is disclosed a trim network suitable to be utilized in monolithic circuits and a method of trimming thereof to improve performance of the circuits to achieve greater yields. The network comprises at least one monolithic resistor connected across a known voltage potential and including a plurality of contacts thereon defining incremental resistances therebetween. The contacts are coupled to a common terminal via a plurality of metallic links. A desired output voltage is derived at the common terminal by open circuiting all of the links but a desired one. The voltage appearing at the common terminal can then be used for trimming a parameter of the monolithic circuit to improve the performance thereof.

Trim network for monolithic circuits and use in trimming a d/a converter

An adjustable impedance network is disclosed which is suitable to be used in monolithic circuit applications to eliminate problems caused by processing tolerances. One example of such use is to employ the impedance network in the collector circuit of a differential amplifier to eliminate input voltage offset errors. The impedance network includes a plurality of impedance elements serially coupled together between first and second terminals which in the above example would be coupled to respective collector output electrodes of the differential amplifier. Each impedance element is initially electrically shorted by a respective one of a plurality of thermally machinable metallic link. In addition, a selected number of the impedance elements are electrically shorted to a common terminal by two additional metal links which are serially connected together across said selected number of impedance elements. The impedance elements are binary weighted to provide a maximum number of trim values. A laser apparatus may be used to cut or machine appropriate links to open circuit the link to add predetermined resistance between either the first or second terminal of the network and the common terminal thereof. Thus, in the above example, resistance may be added to either collector load resistor of the differential amplifier to compensate for mismatch in the transistors comprising the amplifier.

Impedance trim network for use in integrated circuit applications

A plurality of inverted transitor current mirror and pull down circuits are disclosed which are suitable for providing current mirroring and base pull down functions in a variety of integrated circuit applications. The use of the inverted transistor as a current mirror is also utilized in gaining and/or level shifting any differential or single-ended analog or digital signal. The use of a multiple emitter inverted transistor for providing multiple pull down reduces to a fraction the chip area otherwise required by the use of multiple transistors.

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Mesa, AZ, United States of America

John J Price